Lab 4 - ECE 421L 

Authored by Fred Hathaway,

hathawa6@unlv.nevada.edu

27 Sept 2013 

  

Lab 4: IV Characteristics of NMOS and PMOS devices in ON's C5 process:

 

I Created a new cell for the NMOS device schematic.  Select Cell -> New Cell from the menu.  I called the new cell "NMOS_IV".  I selected the NMOS node from the component list.


NMOS2.JPG

Next I edited the device properties (CTRL_I).  

NMOS_fig1.JPG

 I changed the width to 10 and the length is set to 2.  


NMOS_fig2.JPG

Next I selcted the NMOS node and went to Tools -> Siulation (Spice) -> Set Spice Model.  We can rotate the text as desired through the device properties.  I chose to leave a 0 degrees orientation.  I used the device prperty menu and changed the "Spice Model" to the one for our design which in this case is "NMOS".  

NMOS_fig3.JPG

   

Once the device properties are set I cleaned up the schematice by placing the text next to the device.  At this time I created three nodes (from component menu) and labeled the D,G and S as shown below.  Additionally, the ground is placed as seen below.

 

NMOS.JPG

 

I repeated the same steps above for the PMOS device.  The nodes are labels D,G and S for both schematics.  Notice that the width is 20 and the length is 2 for the PMOS device.

 

 

PMOS1.JPG

 

Added the wire and exports.  Added the "Spice Model" and changed it to "PMOS" in the device properties menu.

 

PMOS2.JPG

 

Next I labled the exports S, G and D as seen below.

 

  PMOS3.JPG

 

VDD was added to complete the schematic as seen below:

 

PMOS4.JPG

 


 

Next, I created a new cells for the layouts for both the NMOS and PMOS devices.  Again go to Cell -> New Cell and click on layout and don't forget to name your cell "NMOS_IV" and "PMOS_IV"

 

Once the new cells are created begin by selecting the nMOS node from the component menu.

 

NMOS_layout1.JPG

 

 Next add nAct Nodes as seen below.  These will be the source and drain connections for the MOSFET that we are creating.  

 

NMOS_layout2.JPG

 

Next add metal1 contact to poly1 as seen below.  This will connect the metal1 to the MOSFETs gate terminal.  Additionally,  select the pWell Node for the body connection.  Your layout should look like this now:

NMOS_layout3.JPG

Select the nMOS node and click Edit -> Properties -> Object Properties (or CTRL_I).  Set the width to 10 like we did in the schematics.  Next with the nMOS node still selected go to Tool -> Simulation (Spice) -> Set Spice Model.  Set the Spice model and change it to NMOS to match the schematic that we created earlier.  Also, make sure you change the text size to a readable size like 2.

NMOS_layout4.JPG

We also need to change the size of the nAct Nodes.  You can select both by first selecting one and the hold shift while selected the second node.  Edit properties with CTRL-I.  Change the X size to 10.  We also need to change the size of the pWell node.

NMOS_layout5.JPG  

Next, we need to connect the nMOS node to the nAct node.  Do this by left clicking on the nMOS node and righ clicking on the nAct node.  Do the same for the other nAct node.  Change the width of the arc to 10 and select Neither End for the End Extension..  Results are seen below:  

NMOS_layout6.JPG 


Now move the top and bottom nAct node into place:

NMOS_layout7.JPG

Make sure you check for DRC errrors (F5).  If you have any errors, make sure you correct them.

Next we will connect the gate of the MOSFET to the poly1 to metal1 node.  Once connected I had to change the width to 2 in order for the arc to match the width of the nMOS node.  

NMOS_layout8.JPG

At this time when we do a ERC Well Check (Tools -> ERC -> Well Check) we will get two errors.  This is because there is no well contact to the p-well surround the NMOS device and the pWell node is not connected to ground.  

NMOS_layout9.JPG

Move the pWell node over so that it overlaps the nMOS pWell layer.  Now do another Well Check and ensure there are no errors.

 

 NMOS_layout10.JPG

Next lets connect the substrate to ground.  Left click on the pWell node and right click below to create an arc.  Create an export (CTRL_E) and label it gnd.

NMOS_layout11.JPG

 

Next add metal1 arcs to the other 3 terminals and create exports as well.  Check for DRC and well errors.

NMOS_layout12.JPG

3-D view of the NMOS device:

NMOS_3d.JPG

Save the library.  Next create the PMOS_IV layout in a similar fashion.  Select pMOS node, 2 pAct nodes, nWell node and metal1 to poly1 contact.  

PMOS_layout1.JPG

Below is the PMOS layout with the exports ( D, G, S and vdd).

PMOS_layout2.JPG

3-D view of the PMOS device:
PMOS_3d.JPG
Next I created simulation cell for the NMOS device as seen below.  The wires are labels and not exported.

simNMOS_cell.JPG
 
and a simulation cell for the PMOS device. Again the wires are labeled and not exported:
 
simPMOS_cell.JPG

Next, I created icons for my design to simplify the look of the schematic.  To create an icon select your schematic that you created for the NMOS device, go to View -> Make Icon View.   

NMOS_icon1.JPG

A generic box appears in the corner of the schematic.  You enter the icon view my selecting the icon and press CTRL-D.  This will enter the icon editor.  Here I selected created the icon using the various shapes from the component list.  Once I drafted the icon the way that I wanted, I moved the exported over and placed them in the correct orientation.  Below is my NMOS icon design:

NMOS_icon2.JPG

Now that the icon for the NMOS device is completed.  I can use the icon in my simulation schematic seen below:

NMOS_sim_icon.JPG

 

The simulation results for the NMOS device:

NMOS_sim_results.JPG

PMOS icon:
PMOS_icon1.JPG

I also used my PMOS icon in my simulation schematic.  The look is much better now:

PMOS_sim_icon.JPG

PMOS simulation results:

PMOS_sim_results.JPG

I backed up my lab work by archiving directory, emailing and posting on the cmosedu website.

Copy of lab4_Hathaway.jelib file
 
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