Lab 7 - EE 421L
Authored
by: Kendrick De La Pena
Date: October 18, 2013
Email: delape19@unlv.nevada.edu
Lab Description
Lab 7 will focus on using buses and arrays to the design of word inverters, muxes, and high-speed adders
Lab Work
8-bit Inverter
Using buses, we can create an 8-bit inverter as shown below
We can simulate the inverter to show the multiple inputs and outputs
8-bit Gates
Similarly, buses can be used to create 8 bit gates. The following shown are: NAND, NOR, AND, and OR gates
The
following is a simulation involving all gates in one schematic. B is
equal to 10101011, and A is equal to 11111111 or 00000000
For
the OR and NOR gate, A is equal to 11111111. As a result, the output
for NOR is 00000000 while the output for OR is 11111111. For the AND
and NAND gate, A is equal to 00000000. Thus, the output for NAND is
11111111 while the output for AND is 00000000
2-to-1 Demux
A Demux acts as a selector for to different inputs. The schematic is shown below (the power and ground was added but not shown)
The
following shows how a demux works. If S equals 1, then A or 1 is
chosen. If S equals 0, which means S inverse is 1, then B or 0 is chosen
Using
buses, we can create an 8-bit demux. With an inverter, we no longer
need an S inverse. Rather, we just use S and use the inverter to get
the complement
Full Adder
Below is an alternative schematic for a full adder. Its function is the same
The following is a layout of the full adder
We can creat an 8-bit full adder with the use of buses
The following shows how the adder will work.
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