Lab 6 - EE 421L
Authored
by: Kendrick De La Pena
Date: October 13, 2013
Email: delape19@unlv.nevada.edu
Lab Description
Lab 6 will focus on the design, layout, and simulation of a NAND gate, NOR gate, XOR gate, and a Full Adder.
Lab Work
NAND gate
A NAND gate can be made using 2 PMOS devices and 2 NMOS devices. The icon view is at the top of the schematic
![00%20NAND%20Schematic.JPG](00%20NAND%20Schematic.JPG)
The
layout matches the schematic. A standard cell frame, or an sframe, of
110 was used. The sframe is made larger for more complicated designs. All checks were made with not errors present.
![01%20NAND%20Layout.JPG](01%20NAND%20Layout.JPG)
Using
the icon view, a small circuit is created to test the input and output.
The graph is shown with all possible inputs as well as an IRSIM.
![02%20NAND%20Circuit.JPG](02%20NAND%20Circuit.JPG)
![03%20NAND%20Graph.JPG](03%20NAND%20Graph.JPG)
![03%20NAND%20IRSIM.JPG](03%20NAND%20IRSIM.JPG)
NOR gate
A
NOR gate can be made using the same MOSFETs as a NAND gate but
connected differently. Also, the PMOS devices are 20/2 instead of 10/2.
![04%20NOR%20Schematic.JPG](04%20NOR%20Schematic.JPG)
Layout is as follows. All checks were made.
![05%20NOR%20Layout.JPG](05%20NOR%20Layout.JPG)
Schematic and graphs are below
![06%20NOR%20Circuit.JPG](06%20NOR%20Circuit.JPG)
![07%20NOR%20Graph.JPG](07%20NOR%20Graph.JPG)
![07%20NOR%20IRSIM.JPG](07%20NOR%20IRSIM.JPG)
XOR gate
An
XOR gate can be made with four 20/2 PMOS devices and four 10/2 NMOS
devices. However, since the gate requires inverse inputs, two more of
each device are needed, totaling to six PMOS devices and six NMOS
devices.
![08%20XOR%20Schematic.JPG](08%20XOR%20Schematic.JPG)
Layout is as follows. All checks were made.
![09%20XOR%20Layout.JPG](09%20XOR%20Layout.JPG)
Schematic and graphs are as follows
![10%20XOR%20Circuit.JPG](10%20XOR%20Circuit.JPG)
![11%20XOR%20Graph.JPG](11%20XOR%20Graph.JPG)
![11%20XOR%20IRSIM.JPG](11%20XOR%20IRSIM.JPG)
Full Adder
A
full adder can be implemented in two ways. The first way is with three
AND gates, 1 OR gate, and 2 XOR gates. Since we made NAND and NOR
gates, four inverters will be needed to implement the adder in this way.
![12%20Fadd1%20Schem.JPG](12%20Fadd1%20Schem.JPG)
A small circuit is made to show all possible inputs and outputs.
![12%20Fadd1%20Schem.JPG](12%20Fadd1%20Circuit.JPG)
![12%20Fadd1%20Graph.JPG](12%20Fadd1%20Graph.JPG)
![12%20Fadd1%20IRSIM.JPG](12%20Fadd1%20IRSIM.JPG)
A
full adder can also be implemented with three NAND gates and two XOR
gates. The same steps were taken with the addition of a layout.
![12%20Fadd2%20Schem.JPG](12%20Fadd2%20Schem.JPG)
![12%20Fadd2%20Schem.JPG](12%20Fadd2%20Layout.JPG)
Circuit and graphs are below.
![12%20Fadd2%20Circuit.JPG](12%20Fadd2%20Circuit.JPG)
![12%20Fadd2%20Graph.JPG](12%20Fadd2%20Graph.JPG)
![12%20Fadd2%20Graph.JPG](12%20Fadd2%20IRSIM.JPG)
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