Lab 4 - EE 421L 

Authored by: Kendrick De La Pena

Date: September 25, 2013

Email: delape19@unlv.nevada.edu

Lab Description

Lab 4 will focus on the IV characteristics of NMOS and PMOS devices in ON's C5 process.

PreLab Work

Tutorial 2 was completed as given on the main site.

Lab Work

1) In the schematic, a NMOS transistor was used as the body with off-page nodes exported to D, G, and S. A ground was placed to match with the ground of the layout. The layout of NMOS consists of the NMOS node, 2 nAct nodes, a metal1 to contact to poly 1, and a pWell node for the body connection. The NMOS has characterisitcs of 10/2. 

2) In the schematic, a PMOS transistor was used as the body with off-page nodes exported to D, G, and S. A power node was placed to match with vdd in the layout. The layout of the PMOS consists of the PMOS node, 2 pAct nodes, a metal1 to contact to poly 1, and a nWell node for the body connection. The PMOS has characterisitcs of 20/2.

A spice code was used for the simulation. As shown, the source currents for various VGS values went in a negative direction.

3) In both schematics for NMOS and PMOS, the schematics are in an awkward view. Using the "Make Icon View" in the menu, you can get rid of the floating power/ground, leaving only the connecting wires. 

Return to Kendrick's labs