Lab Project - EE 421L 

Authored by Chad Johnson,

ctjohnso@unlv.nevada.edu

11/7/13 

 

For the final project for this lab I will be laying out a simple arithmetic logic unit (ALU). The ALU will have 4 operations and 2 8-bit operands. I have selected the following control signals for my ALU.

 

 

 

Most of the components of the ALU have been created in other labs, so now it will be a task of assembling the ALU. 2 8-bit 2 to 1 demuxs will be used to select either the output from A or B, A and B, or the output from the 8 bit full adder. The 8-bit full adder performs either addition by inputting A, B, and Cin=0, or subtraction by inputting A, B', and Cin=1. This setup is accomplished by inputting the F1 control signal into both the Cin for the full adder as well as using it for a control signal for the 8-bit demux (thus selecting B' for each input into the full adder). It is observed that this setup essentially takes the 2's complement of B (B is inverted and Cin=1 essentially adds 1). The schematic is constructed as shown below.

 

 

I needed to resolve an issue with the 8 bit 2 to 1 demuxs to get them working correctly. Namely, control signals of zero were not selecting the top input, which is logical. Upon resolving this issue, I proceeded to try a few different IRsim stimuli to ensure correct operation. First I let A = 50 (0x32) and B = 56 (0x38). I deliberately selected numbers that would result in a negative number at the output for the A-B operation. The IRsim confirmed the ALU's functionality for these inputs as shown below. The stimulus for this simulation is found in proj/proj_electric_files/ALU_sim_Aequals50_Bequals56.

 

 

This produces the correct result for A OR B (=0x3A), A AND B (=0x30), A+B(=0x6A), A-B(0xFA).

 
Although I felt this simulation had good variety and likely proved correct functionality, I felt it was diligent to try one more input combination. Thus, all 4 operations were performed with inputs A = 72 and B = 12. The results of this simulation are shown below. The stimulus for this simulation is found in proj/proj_electric_files/ALU_sim_Aequals72_Bequals12.
 

 

Again the outputs match hand calculations (A OR B = 0x4C,  A AND B = 0x08, A + B = 0x54, A - B = 0x3C).

  

It is possible that IRsim is not catching some flaw that a Spice simulation would catch. Thus it would be diligent to test functionality in a spice simulation. Thus the operation is checked for a third time with spice. Shown below is the spice simulation circuit and simulation results. This simulation is found in the project jelib in a schematic named "alu_spicesim". 

 

 

 

 

 
Thus the ALU operation has been confirmed in both IRsim and LTSpice with different input values.
 
Next I proceeded to layout the ALU. This required careful planning, constant DRC and Well Checking, and a little debugging before getting the ALU to function properly. The layout is shown below.
 

 
The different portions of the layout are labeled in the figure below.
 
Thus

The layout passed NCC, DRC, and Well Checks. The results of these checks is shown below.
 

 

 This concludes my ALU design. As always I back up my work.

 

 

The Electric files for the project are found here and here.

 

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