Lab 5 - EE 421L
Shown below is the layout, schematic, and icon for the 100/50 inverter.
Simulation yielded the following results. Note that the outputs of the inverters are nearly idential
Next the capacitive load was increased to 1 pF. The schematic and spice simulation are shown below.
Next I use the built in simulators IRsim and ALS. First we simulate with ALS. We note that ALS is simulates only logic and doesn't consider transistor level non-idealities. Thus the ALS simulation does not consider the delay from the capacitive load.
We note that the ALS does not consider the capacitive load and the simulations are insensitive to changes in the capacitive load.
Shown
below is the simulation circuit and results of the IRsim simulation.
The IRsimulation includes the considerations and non-idealities of
transistor level design. Thus it is capable of demonstrating the
delays associated with the circuit. Shown below is the circuits and
simulations with the different capacitive loads.
It is clear that IRsim considers the higher capacitive load unlike ALS which ignores it. The 10pf load clearly takes longer to respond to the change in the input.
This concludes the lab work. I back up my work as shown below.