Lab 2 - EE 421L 

Authored by Chad Johnson,

ctjohnso@unlv.nevada.edu

9 6 13

    

In this lab we will design a 10-bit DAC using an n-well resistance of 10k and compare its functionality to an ideal DAC.  Further, we will attempt to predict the delay the DAC has driving a 10pF load. Lastly, we will try to compare the functionality of our DAC driving a 10k load to one driving to the ideal DAC.

   
Prelab Work:
   
First, download lab2.jelib which contains an ideal 10-bit ADC as well as an ideal 10-bit DAC. Open this file with electric and perform a Cross-Library Copy to place these models and their simulations into the working directory for the lab.
   

   
Now our working library contains the ADC and DAC along with their simulations. To demonstrate their functionality, select the sim_ADC_DAC cell and simulate. You should see the following.
   
 

We see that the output has lost precision from input. This occurs because when the signal is converted to a digital signal, it is only able to store with precision equal to the voltage range of its least significant bit. To determine this voltage across the least significant bit, we zoom in on the simulation and determine that 1 LSB represents. Note that when we design the DAC for the lab we will determine the voltage with VDD/2^n, where n is the number of bits.
 


Lab 2 - Design and Simulation of DAC:
   
Next the non-ideal Digital to Analog converter is drawn up in Electric.  The design is shown below.
   
 
   
This device is added to a duplicate cell of the simulation performed on the ideal DAC. Note that it was necessary to reroute the pins B9:B0 since the routing was not automatic. We note that this design passed the design rule check.
   
We note that the output resistance of the DAC is R. Logically, as we step up the DAC from the least significant bit, we note that we seem to, in each increment, return to the calculation of 2R || 2R = 1R. Thus, it is clear that the output resistance, if you keep creating parallel combinations of resistors, will be equal to R (10k in this particular design).
   
It was observed that the non-ideal DAC matched up very well with the ideal DAC when not driving a load. However, the finite output resistance makes the non-ideal DAC's output vary with a load impedance.
   
A 10pf capacitor is attached to the output of the non-ideal DAC in the schematic seen below. Hand calculations put the delay time for charging the capacitive load at .7 * R * C = .7 * 10 * 10^3 * 10 * 10^(-12) = 70 ns.
   
   
   
In the simulation of this schematic, it is shown that the estimated delay time of 70ns is reasonable.
   
   
Next we will look at how the DAC reacts with no load, a capacitive load, a resistive load, and a resistive and capacitive load. First lets have a look at vout when it is unloaded.
   
      
We observe that it acts very much like the ideal DAC when it is not driving a load. Next we observe the effects of a purely capacitive load.
   
   
We note that the capacitance causes the output to lag the input (RC time constant was computed above). Next lets observe the non ideal DAC driving a purely resistive load.
   
   
We observe that the finite output resist created a voltage divider with the 10k resistive load and reduced the output voltage by a factor of a half. Lastly, we look at the effects of the non ideal DAC driving a resistive and capacitive load.
   
    
We observe the voltage reducing effects of the resistive load as well as the time delay effects of the capacitive load.
   
When the switches of the DAC are implemented with MOSFETS, it is necessary that the resistance of the MOSFETS be small compared to the values of the resistor, else the accuracy of the DAC will be compromised by the resistance of the MOSFETS causing unintended voltage drops.

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