Lab 2 - ECE 421L 

Authored by Ken Adams,

Today's 6 September 2013

Lab description

We need to import the appropriate libraries for this lab.

• Back-up all of your work from the lab and the course.
• Download the lab2.jelib which contains a simulation example using an ideal 10-bit Analog-to-Digital Converter (ADC) and 10-bit DAC.
• Open, using Electric, your lab/course jelib (below this is ee421_ecg621.jelib) and the lab2.jelib you just downloaded
• Use the Electric menu command Cell -> Cross-Library Copy...
• The cell sim_ADC_DAC{sch} contains the ideal 10-bit ADC and DAC. 
• Copy sim_ADC_DAC{sch}, all of its subcells, and all related views into your lab/course jelib

• When finished hit "Done" and then close the lab2.jelib in Electric's Explorer so that only the course/lab jelib is open as seen below
• Next Save your course/lab jelib (circled floppy disk seen below)
• Your course/lab jelib should now also contain the copied cells related to the ideal 10-bit ADC and DAC
• Backup this library

 A R-2R ladder Digital to Analog converter will be laid out. We want to use the ideal DAC symbol for our R2R implementation.

Create a new cell layout and name it R2R_DAC or something similar. Copy the ideal DAC into your library. Rename the ideal DAC symbol and schematic to R2R or something similar. Open the symbol with CTRL+D and remove everything expect the following:

 We are no ready to construct the R2R DAC ladder. Each bit of the ladder has the following form:

 Notice the implementation of of the 20k (2R) resister as two-10k resistors in series. We are making a 10bit DAC so we will copy this 10 times:

a

 Notice the 20k (2R) resistor at the bottom. Our full symbol of our R2R_DAC should look like:

 Make sure to DRC the design. Edit -> Cell Cleanup -> Clean all (default F4) can be useful to clean extra pins. After the DRC passes, we want to test our DAC. We will use the digital input of our DAC as the output from the ideal ADC:

 Simulate the design and you should get the expected ADC to DAC waveform:

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