EE 420L – Engineering Electronics II Lab – Lab 3

Authored by James Skelly

Email: skellj1@unlv.nevada.edu

Due: February 20, 2019

  

Lab Description

·        Breadboard implementation of basic op-amp topologies, testing finite gain and offset.

 

 

Pre-Lab

·        Watch the op-amps discussion video.

·        Simulate the op-amp circuits found in the op-amps zip file.

·        Review basic op-amp circuits.

·        Read the lab write-up before coming to lab.

 

 

Lab Tasks

 

This lab will utilize the LM324 op-amp (LM324.pdf).

For this lab, it was assumed that VCC+ = +5V and VCC- = 0V.

 

 

Explain how the following circuit can be used to measure the op-amp's offset voltage.

 

·         Note that all of the above questions are answered in the text of this lab report.

 

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Preliminary Questions from LM324 Datasheet Analysis

1.)         Knowing the non-inverting input, Vp, is at the same potential as the inverting input, Vm, (called the common-mode voltage, VCM) what are the maximum and minimum allowable common-mode voltages?

 

 

§  From the datasheet, we see above that minimum value for VCM at nominal temperature is 0V.

§  For maximum VCM, we can calculate based on our +5V VCC used in the lab. VCM(max) = 5V – 1.5V = 3.5V.

 

 

2.)        What is a good estimate for the op-amp's open-loop gain? 

a.   Support your answer with a plot from the datasheet and an entry from the electrical characteristics table.

 

 

§  The above portion of the datasheet shows us that minimum gain is around 50V/mV, and typical gain is around 100V/mV.

§  Taking the typical value, a good estimate for the op-amp’s open-loop gain is 100V/mV.

 

From this plot found in the datasheet, we see that open-loop gain changes with increasing power supply voltage.

Because we are using a power supply voltage of 5V, reading from the plot, we expect an AOL of around 110 dB.

 

 

 

This plot from the datasheet shows us that at 0 Hz (or DC) the open loop gain of the circuit is right around 110 db.

Given this value, the open loop gain of the op-amp can be calculated by:

 

     

 

 

3.)        What is a good estimate for the offset voltage? 

§  For worst case design what value would you use?

 

 

From the datasheet, we see that at nominal operating temperature (25 degrees Celsius), for the LM324, we can expect a typical offset voltage of 2mV.

Also from the data sheet, we can see that at high operating temperatures, we can expect a 9mV offset voltage.

Therefore, for worst case design, 9mV should be accounted for, assuming that temperature of operation will not always be ideal.

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Circuit 1: Inverting Topology with Gain = -1

For LTspice simulations in this lab report, I imported the LM324 spice model into LTspice for more accurate simulation results.

For the inverting topology below, the ideal gain is equal to -RF/RI. Therefore, the ideal closed-loop gain in this circuit is -1.

 

 

The schematic above shows a DC circuit with input VDD = 5V and output VCM, the common-mode voltage of the op-amp, 2.5V. The common mode voltage is typically ((V+) + (V-))/2, which in this case is (5V – 0V)/2 or 2.5V. Common-mode voltage acts as a reference in an integrated circuit like an op-amp. Note that power supply voltages for this experiment are V+ = 5V and V- = 0V. We need the common-mode voltage, our reference, to be in the middle of V+ and V- so that we can use the full output range or output swing of the op-amp for AC signals. (Full output swing of the op-amp is 0V to 5V, and it is centered around VCM=2.5V) If we were to input a sinusoidal voltage with no DC offset and a common-mode voltage of zero, the signal would clip and we would only get the positive part of the sine wave as an input signal. Having VCM at 2.5V allows us to use the full output voltage range of the op-amp.

 

Note also that in this circuit, VCM does not change. Small decoupling capacitors are placed on both the input and the output of the common-mode voltage DC circuit to ensure that neither VDD nor VCM change. We know that for DC circuits, a capacitor will act as an open. Therefore, no current will flow through the capacitors, and the voltage divider will operate as if the capacitors were not even there. However, the capacitors will still charge up (C1 to 5V and C2 to 2.5V) and will remain charged after 5 time constants once the circuit is “turned on” or power is given to the circuit. Once these capacitors are charged, they will not discharge until the circuit powers down. As long as the circuit is being powered, thanks to the decoupling capacitors, VCM will not change. Note that the value of capacitors is not critical. Smaller or larger capacitors could be used, because regardless of the size of the capacitor, no current will be flowing through it in the DC circuit. Larger capacitors would simply take longer to charge up on start-up, and smaller capacitors would take less time to charge up, but overall the size of these capacitors is not critical, as they are simply there to maintain the voltage at VDD and VCM.

 

 

Recalling that the ideal closed-loop gain of the inverting amplifier topology above is -1, we observe the expected simulation results. For AC signals, inverting is simply phase-shifting by 180 degrees. The input to our circuit is a 100mV amplitude sine wave oscillating around 2.5V (due to a 2.5V DC offset) at 1 kHz. We expect the output to be the same signal, but out of phase by 180 degrees, and that is exactly what we see here. 

 

 

Above is a photo of the breadboard implementation of the circuit simulated previously. The pin connection diagram was used from the LM324.pdf data sheet in order to make the proper connections.

 

 

Here we see that the experimental output of the circuit matches our simulated output almost perfectly, with the signals out of phase by roughly 180 degrees, as measured by the scope.

 

 

Examining Input Bias Current, Offset Current

Using the LM324 spice model, we do not have to model the 20 nA input bias current using a current source because the spice model has that parameter already included.

 

R1 = R2 = 10k

 

Below, we see the operation of the op-amp with R1 and R2, the voltage divider resistors to obtain VCM, at 10k.

 

 

 

The input bias current, as is mentioned in the question above, flows out of both the inverting and non-inverting inputs to the op-amp. This means that the current will flow into net VCM. Now, in the circuit above, we have VCM = 2.5V dropped across a 10k resistor. By Ohm’s law,

                                                                                                     

 

With 250 µA flowing through R1, the 20 nA input bias current is negligible, because it is very tiny in comparison to the magnitude of the already-flowing current.

 

 

R1 = R2 = 10 MEG

 

Below, we see the operation of the op-amp with R1 and R2 set to 10 MEG.

 

 

 

Here, we can take the DC circuit to solve for VCM using superposition. To find the initial current flowing in the circuit neglecting input bias current, we simply use Ohm’s law around the resistive divider to get

                       

 

We can then model the input bias current by shorting the VDD voltage source and sending a 20 nA current into net VCM. The two resistors can be connected in parallel, and with the same potential on either side of both resistors, the current I2 is just 20 nA. The new current flowing in the circuit including input bias current is 250 nA + 20 nA, or 270 nA.

 

We can then solve for the new VCM value by the equation below, which is verified by plotting VCM in spice for the circuit above.

           

 

 

Finally, with a new value for VCM, Vout will also change, as we saw above. Using KCL,

 

            , where Vm = VCM = 2.7 V

 

           

 

From the simulation, we see that our calculation is verified, and the output swings around roughly 3V.

 

 

From the above calculations and simulations, we can conclude that the input bias current is negligible for smaller resistance values, but for larger resistance values, the input bias current is closer to the current flowing in the actual circuit, and will no longer be negligible. In fact, it will have large effects on both VCM and Vout as a result.

 

In short, the offset voltage is a parasitic (unwanted) voltage on the inverting or non-inverting input that leads an op-amp away from ideal operation by making Vp not equal to Vm. The input offset current is the current that flows as a consequence of this offset voltage. For some potential VOS (Voffset) there will be a consequential input offset current that flows into the terminal of the op-amp that the offset potential powers. 

 

Clipping Output Simulations and Experimental Results for Gain = -1

 

·         From the datasheet, as we can observe above, the maximum value input common mode voltage is VCC -1.5V. This means that for common mode voltage of 3.5V (max VCM) the maximum input signal can reach peak voltages of 5V without the output clipping for a topology designed with a gain of +/- 1. However, for this lab, we are using a VCM of 2.5V rather than 3.5V, so our maximum input signal will be 1V lower than VCC, or 4V. From the following simulations and experimental results, we observe the output clipping for input signals greater than 4V peak (adding the offset voltage to the amplitude).

 

Simulations

 

  

·         We observe from the above simulation that the output begins to clip for an input signal with a peak voltage around 4 to 4.1 V. Therefore, according to simulations, the maximum input signal for the circuit with a gain of -1 is 3 to 3.2 Vpp with a DC offset of 2.5V. The simulation below shows that as we increase the peak voltage of the input signal, the output continues to clip at right around 4 V.

 

  

 

Experimental Results

 

  

·         The experimental results above show that for a peak-to-peak voltage of 2.5 V (Vpeak = 1.25V) and a DC offset of 2.5V, the output clips at around 3.75V, which varies slightly from the maximum voltage we saw in the previous simulations (4V). The results below show, again, that as we increase the amplitude of the input signal the output continues to clip at around 3.75V.

 

  

 

 

Clipping Output Simulations and Experimental Results for Gain = -10

 

Simulation of Op-Amp Circuit with gain of -10, operating as expected. The output is an inverted version of the input.

 

 

 

·         Below, in order to show the gain, the traces are separated and the DC offset is subtracted from the output. We see here that the output is clipping for a much smaller input signal than before. This is because the gain now has a magnitude of ten, so the max input signal should ideally be ten times smaller. Previously, we had a maximum input signal with a 1.6V peak and a DC offset of 2.5 V. We see here that for a signal roughly ten times smaller, the output clips. The maximum input signal for this circuit would be a signal with a DC offset of 2.5 V and a peak voltage around 160 to 170 mV.

 

 

·         Below, we see that increasing the peak voltage to 200 mV, output signal clips even more, as expected.

 

 

Experimental Results

 

Experimental Op-Amp Circuit with gain of -10, operating as expected. The output is an inverted version of the input.

 

 

 

·         The peak voltage of the input signal is the DC offset plus half of the peak-to-peak value on the function generator. Peak to peak voltage measures from peak to trough of the waveform, while amplitude is only half of the peak-to-peak value. Therefore, for a Vpp=330mV as seen below, the amplitude of the waveform is 165mV, or half of Vpp. This is the expected value for output clipping. Our simulations led us to the conclusion that the maximum input signal would be a signal with a DC offset of 2.5V, and an amplitude between 160 and 170mV.

 

 

·         Further increasing the amplitude makes the output clip even more, as expected.

 

 

 

Circuit 2: Inverting Topology with Gain = -20, Measuring Offset Voltage

 

Below, we can see the test setup used to measure VCM and Vout to solve for offset voltage of the four different op-amps.

 

 

VCM is fed directly into Vp and into the 1k resistor on Vm. Ideally, Vm should be equal to VCM, because in an ideal op-amp, the plus terminal and the minus terminal are at equal potential. However, in this circuit, if there is some offset voltage, then Vm will not be equal to VCM, and that offset voltage will be dropped across RI, and amplified by the closed-loop gain of the circuit. We can then measure VCM, measure Vout, take the difference between the two, and divide by the gain to get the true offset voltage.

 

 

 

Using a multimeter, VCM and Vout were probed with respect to ground for each of the four op-amps that were tested.

 

 

LM324 Offset Voltage Measurements Using Multimeter

 

VCM Measurement

Vout Measurement

 

 

 

LM348 Offset Voltage Measurements Using Multimeter

VCM Measurement

Vout Measurement

 

 

 

LM339 Offset Voltage Measurements Using Multimeter

VCM Measurement

Vout Measurement

 

 

 

LM741 Offset Voltage Measurements Using Multimeter

VCM Measurement

Vout Measurement

 

 

The table below was obtained.  

 

Op-Amp

VCM(V)

Vout(V)

Difference(V)

Gain

Offset Voltage(mV)

LM324

2.5235

2.4647

0.0578

-20

-2.890

LM348

2.5320

2.8911

-0.3591

-200

1.795

LM339

2.5236

2.4734

0.0502

-20

-2.505

LM741

2.5300

2.8827

-0.3527

-200

1.763

 

Note that for the LM324 and the LM339, the inverting topology was used with a gain of -20, achieved using resistors RI=1k and RF=20k.

Note also that for the LM348 and LM741, the inverting topology was used with a gain of -200, achieved using resistors RI=1k and RF=200k.

Recall from the datasheet questions at the beginning of the lab that at nominal operating temperature, the typical offset voltage of the LM324 was 2mV (this can be plus or minus 2mV). From our experimentation, using an op-amp topology with a gain of -20, we get -2.89mV of offset. This matches the datasheet typical value quite well.

 

Analyzing the table above, anyone who wants to use an op-amp in the design of a project on a breadboard would be well off using any of the op-amps tested. Their offset voltages are all between 1.5 mV and 3 mV.

 

 

 

 

 

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