Lab 5 - EE 420L 

Authored by Jacob Reed

reedj35@unlv.nevada.edu

Due Date: March 13, 2019

  

Again, this lab will utilize the LM324 op-amp (LM324.pdf).

For the following questions and experiments assume VCC+ = +5V and VCC- = 0V.

Figure 1: Integrator Circuit

 

Since we are looking at the frequency response of this circuit, we are only looking at the AC components of this circuit.

Therefore, the non-inverting terminal of the op-amp is at 0V (AC).

 

Frequency Response Calculations:

 

The unity frequency of an op-amp is when the gain of the op-amp is equal to 1.

 

it is much larger than R1 and the real term in the denominator goes to zero.

 

The offset voltage is a DC voltage and if there is no resistor in the feedback loop, then there is only the capacitor. The capacitor

acts as an open in a DC circuit and so there will only be a small difference in the inverting input and non-inverting input voltages.

We know that  and so  which will be large and thus, the output voltage will go to the power rails

of either +5V or 0V in our case.

 

o   In this circuit, the 100k resistor does not have much of an effect on the frequency response. This is because when an AC signal is introduced,

the capacitor will start to play a role in the circuit. The 100k resistor has a much larger impedance than the capacitor and so most of the

current flows through the capacitor.

 

 

Figure 2: Integrator Implemenation at unity-gain frequency

Figure 3: Phase difference between input and output

 

 

We can see that there is a time delay of 1.6ms between the input and output waveforms. Knowing the equation to calculate the delay:

 and then rearranging:

                    The calculated value matches the phase shift I was expecting above.

 

o   Assume the input/output frequency is 10 kHz and the output ramp must swing from 1 to 4 V centered around 2.5 V.

 

Referring to Figure 1 above and ignoring the big resistor, we can see the current flowing through R1 is equal to the current flowing

through C1. Therefore, we can say that the potential across the capacitor is just Vout:

 

 

Solving the integral:

 

Since we want the output ramp to swing from 1V to 4V, .

 

Since the output needs to be centered about 2.5V, I will have an input square wave from 0V to 5V with a frequency of 10kHz;

and my Vcm will be 2.5V.

 

For this design, I will be choosing the value for C1 that will keep the value for my resistor relatively small and so that I

may find a capacitor that is readily available in the lab. The capacitor value I will be choosing is

 

With a frequency of 10kHz, the period is 100µs.

 

          Solving for R1:

         

         

The closest resistor value I could find in the lab is 4.3kΩ.

 

Figure 4: Integrator Design with values used

Figure 5: Simulated integrator waveforms

 

Figure 6: Experimental integrator waveforms

 

As said above, the value used for the capacitor help set what resistor I can choose. I chose the capacitor based off of lab availability, and then this helped the resistor be large

enough for the circuit to operate. As can be seen in the experimental waveforms, the change in the output voltage is 2.96V and it is approximately centered about 2.5V. The

DC offset needed to be changed only slightly to help the waveform look like what was calculated. This is because the voltage at the inverting input slightly differed from the

voltage at the non-inverting input.

 

 

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