Lab 9 - EE 420 

Author:    Marco Muñiz

E-mail:     munizm1@unlv.nevada.edu

4/23/2019 

Lab description:

In this lab you may need to use two, or more, CD4007 chips from the same production lot (see date code on the top of chip) to ensure using a BMR to bias a current mirror is possible. If the CD4007 chips are not from the same production lot they will not "match" so current mirrors will not be possible.

• Build your BMR design and characterize it as you did in the pre-lab (if you use two chips ensure that grounds and VDDs of both chips are tied together).
• You expect the BMR to become unstable if there is a large capacitance across the resistor, such as a scope probe (important), so care must be exercised 
  
• Use your BMR to bias, and thus create, a:
• NMOS current mirror 
• PMOS current mirror
• Measure how the current varies through each current mirror as the voltage across the mirror changes.
• Of course the current in the NMOS (PMOS) current mirror goes to zero as the voltage on the drain of the output device moves towards ground (VDD)
• Using these current mirrors drive two gate-drain connected transistors
• For the first experiment use the NMOS current mirror to drive two PMOS gate-drain connected devices. 
• Use the voltages on the gate-drain connection of the two devices to bias a cascode current mirror (characterize this mirror as before)
• For the second experiment switch, that is, use the PMOS current mirror to drive two NMOS gate-drain connected devices.
• Again, use these two voltages to bias an NMOS cascode current mirror then characterize.

Lab:  

Part 1:  

• Build your BMR design and characterize it as you did in the pre-lab (if you use two chips ensure that grounds and VDDs of both chips are tied together).
• You expect the BMR to become unstable if there is a large capacitance across the resistor, such as a scope probe (important), so care must be exercised 

                        (BMR Circuit Schematic)                                                  (Calculations for R1 Value)

In the above hand calculations, we show the process in which the value of R1 is found. However, we did run into some issues witch matching in this lab which we attributed to mischaracterizing our model in the previous lab. To account for this, we adjusted our Kp values in order to get better matching between our simulated and experimental results. In this experiment, we measured the gate voltages on M2(Vbiasn) and M4(Vbiasp), as well as the voltage across the resistor in order to find our Iref. We were originally going to use the ammeter to measure the current in the branch but we ran into issues reading the smaller values. We believe this was due to the meter not being able to register such small currents so we opted to instead read the voltage across the resistor and divided by the resistance to get our current value. 

Recorded value plots:

                       (Vbiasn plot vs. VDD)                                                 (Vbiasp plot vs. VDD)

                                                                                   (Iref plot vs. VDD)  

Simulated Results:

                                                                                              (Vbiasn Plot)

                                                                                        (Vbiasp Plot)

                                                                                           (Iref Plot)

Overall, we saw a large comparison between our pmos devices and our overall current. As we expected, Vbiasn will maintain an almost constant value once reaching the threshold voltage, however, our experimental threshold voltage was a lot higher than expected. On the otherhand, for the Pmos, we expect to see Vbiasp to increase at a linear rate along side VDD. We saw this occur for both our experimental and simulated results with a very similar threshold voltage of 2V. For our current, we expected the current to be roughly 1.1uA but our experimental results were slighly off at around 700nA but our threshold voltage value was close to spot on for Iref, after the adjustments to our previous Kp value.

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Part 2:

• Use your BMR to bias, and thus create, a:
• NMOS current mirror 
• PMOS current mirror

  Current Mirror Schematics:  

                                                                                  (Nmos Current Mirror)

                                                                                 (Pmos current Mirror) 

Experimental Results: 

                            (Nmos Mirror results)                                                                                     (Pmos Mirror results)

Simulated Results:

                                                                                  (Nmos Current Mirror results)

                                                                                    (Pmos Current Mirror results)

For the results in this part, we expect the bias voltage to increase with VDD. However, the data we collected seemed to be slightly off for both of the mirrors, more so the Nmos than the Pmos. We didn't find it necessary to re-adjust our simulation model again because we figured the issue was with the BMR itself. For instance, we might not have chips from the same lot which would contribute to variation or the way we decided to measure the current was not an accurate method to measure. We do know that the BMR is not made to be a stable reference with changes to VDD, so this could also add to the variation, especially in the Nmos mirror.

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Part 3:  

• Using these current mirrors drive two gate-drain connected transistors
• For the first experiment use the NMOS current mirror to drive two PMOS gate-drain connected devices. 
• Use the voltages on the gate-drain connection of the two devices to bias a cascode current mirror (characterize this mirror as before)

                                                                               (Nmos mirror with 2 Pmos load)

                                                                               (Pmos Mirror with 2 Nmos Load) 

Experimental Results:

                                    (Nmos Mirror w/ 2 Pmos Load)                                                                   (Pmos Mirror w/ 2 Nmos Load)

Simulated Results:  

                                                                               (Nmos Mirror w/ 2 Pmos Load sim)

                                                                                 (Pmos Mirror w/ 2 Nmos Load sim)

For these circuits, we can see a slightly larger Drain current for the Nmos with 2 gate-drain connected Pmos load than for the Nmos mirror, in the measured plots. The Pmos mirror varied slightly more than the Nmos mirror in the experiments. However, for the simulations, we can see a better representation of what we would expect to happen, where the current mirrored in the Pmos devices is about half of the current mirrored in the single Nmos Device. We also note that our threshold voltages have increased for both of the current mirrors, with a 2 volt increase for the Nmos and a 1 volt increase for our Pmos.  

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Conclusion: 

For this lab, we ran into a few issues when first setting how to measure our currents. Specifically, we originally were trying to measure the drain current by placing an ammeter in series with measuring point but due to the current being so low, we were not able to get accurate measurements with it. We opted to place a resistor in series with the drain and measuing the voltage across it with the multimeter and dividing by the resistance to get our current value. We also ran into issues with comparisons between our BMR's experimental and simulated results. We attributed this to a mis-characterization in our MOSFET model and adjusted our previous KP to a lower value for better matching. Ultimately, this lab showed us many of the issues we can run into when in a real-world design setting where our calculated values may not always match our experimental results or when or models vary from our expected results. 

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