Largest output swing as possible
Can pass a 100Hz signal
As fast as possible driving a 1k load
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Project
In order to meet all of the requirments listed above, the push pull amplifier topology was chosen. The push pull amplifier both syncs current as well as sources the current at other times. The push pull amplifier also allows for a higher output power as power dissipation for the amplifier is higher than either transister.
Image 1: Push pull amplifier topology
The first requirement that will be considered is drawing no more than 1mA of current from the 9V supply voltage with quiescent conditions, no input signal. When desiging the amplifier for this requirement two resistors were added, one to the source of the pmos and the other to the souce of the nmos. The higher resistance added to the circuit allows for less current, but splitting the resistance the sources of both transisters allows for the amplifier to sync current as effectivly as it sources it. The following is the calculations for the resistances and capacitance in the circuit.
Image 2: Resistance and capacitance hand calculations
As it can be seen above the transfer function or gain of the op amp is dependent on the gmp, gmn, RL, R1, and R2. Due to the specifications both the gain and the load resistance are specified so the only adjusting that the designer can do is to the R1 and R2 resisters. After calculating these values the input resistance needed to be found, which was done by the relationship between gain and current. First the Rb resistance is set to a large value and then the Rin resistance can be solved to get the gain of 10 that is required. After all of the values were calculated the following circuit was created for simulations.
Image 3: Push pull amplifier design
After creating the push pull amplifier the requirements were tested for shown in the following simulaitons
Image 4: Queiscent current draw with no load
As seen in the simulation above the value that was designed for was 700uA and the simulation peaks at 708uA, this means that the design could use more current that what is drawn now. The lower current was still used as when the circuits are built experimentally they do not always match the simulations and a buffer was given in case the actual circuit drew more current.
Image 5: Gain of push pull amplifier
From the simulation it can be seen that at 100Hz there is a gain of 20.9dB or a gain of 11, and at 1MHz there is a gain of 23dB or 14. This circuit was built experimentally multiple times and the gain always is lower than what is designed or simulated for, this simulation allows for the drop of gain to be closer to what the desired gain is.
Image 6: Input resistance
The simulation above shows that the input reistance changes at different frequencies du to the equation shown in the hand calculations. Since the input resistance value needed changes with different frequencies it makes the design harder to choose values for.
Image 7: Transient simulation with load
When the push pull amplifer has a load connected it can be seen that the gain is roughly 11.7. This gain is used as stated before in order to allow the experimental cricuit to have some loss of gain and still be around a gain of 10. This could be increased as the experimental values were still very low as what was expected.
Image 8: Max output swing
The maximum output swing can be ween when the input voltage is increased to the powing where the waveform clips to its maximum and minimum values. This can be seen seen in the simulation as a maximum output swing of 3.77V
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In conclusion the experimental values we not what the simulations were showing for a few differnt reasons. The difference could be due to the chips not having the exact charaacterization that the data sheets have so the values are slighly off, this is compounded with all of the capacitors and resistors having variations. These variations can have an effect on the current which dictates the gmn and gmp. For improvements on the circuit a second stage might be used in order to improve the gain of the circuit and allow for an experimental value of 10 to be reached. This has a draw back that increasing to a second stage to increase gain will have a higher simulation gain.