Lab 6 - EE 420L
Lab Report
Part 1: Common Drain Amplifier
Common drain amplifiers are also known as a source follower where the gate terminal acts as the input, the source acts as the output, and the drain is common to both input and output. They are a common collector amplifier and sometimes called a stabilizer. Below is a circuit showing two common drain amplifiers on the right is a pmos and the left is a nmos. For this circuit electrolytic capacitors were used for the 10u capacitors, when using the electrolytic capacitors we put the positive leg toward the MOSFET so that it would act an open for DC, and stopping the capacitor from breaking down.
Image 1: Common Drain Amplifier
The first step of analyzing the circuit above is to hand calculate the gate voltage, the output voltage, the drain current and the gm fo the tranistors for both the nmos and the pmos.
Image 2: Hand Calculations for NMOS
Image 3: Hand Calculatoin for PMOS
After calculating these values they were confirmed by the LTSpice simulations shown below.
Image 4: LTSpice dc operation values confirming hand calculations from Image 2 and Image 3.
The next step of the lab was to hand calculate the gain for each circuit as well as the input and output resistances, as seen below.
Image 5: Hand calculations for gain, input resistance, and output resistance for NMOS.
Image 6: Hand calculations for gain, input resistance, and output resistance for PMOS.
As with the previous hand calculations the values were confirmed by LTSpice simulations.
Image 7: LTSpice simulation showing gain for both NMOS and PMOS
After making the LTSpice simulations and hand calculations it is time to experimentally test all the values, however it should be noted that the lab does not have current probes so input resistance was found in an alternative way. To measure input resistance a resistor was put between Vin and the capacitor acting as a voltage divider, if the calculated resistance value was correct then the voltage at the capacitor should be half, if not then we can recalculate until it is half. When output resistance is measured the calculated resistance is put in series with a capacitor which will be in parallel with the resistor after Vout. If the resistor was calculated correctly then the voltage at the capacitor should be half the output. The Experimental values can be seen in the oscilliscope readings in the table below.
| NMOS | PMOS | |
| Gain |  |  |
| Input Resistance |  |  |
| Output Resistance |  |  |
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Part 2: Common Source Amplifiers
Common source amplifiers have the input through the gate and the output in the drain with the source being common to both drain and gate. They are used asvoltage amplifiers but have a few draw backs: Output resistance not high enough for a transconductance amplifier, and it has a limited high frequency response so it is often routed through a common drain or common gate to get better frequency characteristics. Two common source amplifier circuits can be seen in Image 9, the NMOS on the left and the PMOS on the right.
Image 8: Common source amplifier circuit.
The first step in analysing this circuit is to calculate the gain, input resistance, and output resistance for both the NMOS and PMOS as seen below
Image 9: Hand calculations of gain, input resistance, and output resistance for the NMOS.
Image 10: Hand calculations of gain, input resistance, and output resistance for the PMOS.
Following the hand calculations the values were confirmed with LTSpice simulations seen below.
Image 11: LTSpice simulation of gain for both NMOS and PMOS.
All of the values calculated were then experimentally measured as seen in the oscilliscope readings below.
| NMOS | PMOS | |
| Gain |  |  |
| Input Resistance |  |  |
| Output Resistance |  |  |
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Part 3: Common Gate Amplifiers
A common gate amplifier uses the source of the MOSFET as input, the drain as the output, and the gate as the common for both source and drain. They are often used as current buffer, but normally used because of impedance matching. Two common gate amplifiers can be seen below, the NMOS on the left and the PMOS on the right.
Image 12: Common gate amplifier circuit.
The first step in analysing this circuit is to calculate the gain, input resistance, and output resistance for both the NMOS and PMOS as seen below
Image 13: Hand calculations of gain, input resistance, and output resistance for the NMOS.
Image 14: Hand calculations of gain, input resistance, and output resistance for the PMOS.
Following the hand calculations the values were confirmed with LTSpice simulations seen below.
Image 15: LTSpice simulation of gain for both NMOS and PMOS.
All of the values calculated were then experimentally measured as seen in the oscilliscope readings below.
| NMOS | PMOS | |
| Gain |  |  |
| Input Resistance |  |  |
| Output Resistance |  |  |
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Part 4: Push Pull Amplifier
A push pull amplifier has two tranistors that alternatly supply or absorb current from a load. This design allows for a higher output power then the previous amplifiers, however the design requires a phase splitting component which will make the circuit more complex than the previously amplifiers.A push pull amplifier can bee seen below.
Image 16: Push pull amplifier circuit.
Do you expect this amplifier to be good at sourcing/sinking current? Why or why not?
Yes I believe it will be good at sinking or sourcing current as one of the two transistors will always be on allowing for more flucuation.
What happens to the gain if the 100k resistor is replace wih a 510k resistor? Why?
If the resistor is replaced witha 510k resistor the gain should increase as the current would drop, and the current and gain are inversely proportional.
The first step of solving this circuit is to hand calculate the gain as seen in Image 18.
Image 17: Hand calculated gain of push pull circuit in Image 17.
Next the LTSpice simulations were created to verify that as the resitor was increased so to would the gain.
Image 18: LTSpice simulation of circuit in Image 17.
Image 19: LTSpice simulation of circuit in Image 17 with higher resistor.
Finally the experimental value can be seen in the oscilliscop reading below.
Image 20: Experimental values of Vin and Vout of circuit in Image 17.
The final experiment was extremely difficult to get values that were close, if we ever got the gain to be close to what we calculated the input and output wave would become so distorted that the picture was hard to see. This was the highest gain we could achieve with readable input and output functions.