Lab 9 – EE420L
e-mail: mcdonc4@unlv.nevada.edu
This lab will include:
Part 0: Pre-lab description
Part 1: Measuring Vbiasn
and Vbiasp of a BMR circuit
Part 2: Measuring current through a current
mirror
Part 3: Measuring current through gate-drain
connected transistors
Part 0: Pre-lab description
Pre-lab work:
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This lab will use the level=1 MOSFET model created in lab 8 and,
again, the MOSFETs in the CD4007.pdf CMOS
transistor array.
·
Design and simulate the operation of a BMR that biases the NMOS
devices so that they have a gm of 20 uA/V
o
Use a simple (big) resistor to VDD for the start-up circuit
(explain how the addition of a resistor ensures start-up).
·
When the BMR is operating the current in the big resistor should
be much smaller than the current flowing in each branch of the BMR
·
Write-up, similar to a homework assignment,
your design calculations and simulation results. (This will count as the
pre-lab quiz.)
·
Ensure that you show the following in what you turn in:
o
Hand calculations
o
Operation as VDD is swept from 0 to 10 V
§
Vbiasn should stabilize (be constant) after VDD hits a
minimum value (estimate this value of VDD assuming VGS/VSG is a threshold
voltage and VDS,sat/VSD,sat is zero).
§
Vbiasp should follow VDD after VDD hits a minimum
value (show this in simulations)
o
Unstable operation if too much capacitance is shunting the BMR's
resistor (see bottom of page 630)
o
Comments comparing the hand calculations with the simulation
results
Part
1: Measuring Vbiasn and Vbiasp
of a BMR circuit
In this lab you may need to use two, or more,
CD4007 chips from the same production lot (see date code on the top of chip) to
ensure using a BMR to bias a current mirror is possible. If the CD4007 chips
are not from the same production lot they will not
"match" so current mirrors will not be possible. Build your BMR
design and characterize it as you did in the pre-lab (if you use two chips
ensure that grounds and VDDs of both chips are tied together).
You expect the BMR to become unstable if there is a large capacitance across
the resistor, such as a scope probe (important), so care must be exercised.
We will design of our BMR circuit. The LTSpice model we used to set the parameters of the transistors
is the following:
These parameters were measured results taken
from our previous lab, Lab 8, and made for the CD4007 CMOS IC chips. For this
design we must also choose a resistor R1, which is based on the following
calculations
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Calculations |
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Constants from lab 8:
Resistor R1:
Current:
Saturation range:
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Based on the above calculations we will be using
a 50k resistor.
Upon simulating the above circuit, we sweeped VDD from 0 to 10V to model the behavior of Vbiasn and Vbiasp along with the
behavior of the drain current, ID:
This was expected behavior as we expect Vbiasn to saturate once it reaches a certain VDD along with
a constant rise in Vbiasp. This is reflected in the
simulation. We can also see that Vbiasp follows Vbiasn up until the 1.6V range until it breaks off. This is
reflected in our hand calculations. We hope to see the same results in our
experimental data.
Experimental data:
We used Microsoft excel to plot our data.
For the current we measured the voltage Vref and divided the voltage by an additional resistor we
used to calculate the current.
Given these results we were able to conclude
that our BMR circuit was operating correctly as Vbiasn
leveled off at a certain VDD voltage while Vbiasp and
the drain current continued to increase with increasing VDD.
Part
2: Measuring current through a current mirror
Use your BMR to bias, and thus create, a:
o
NMOS current mirror
o
PMOS current mirror
Measure how the current varies through each
current mirror as the voltage across the mirror changes. Of course, the current
in the NMOS (PMOS) current mirror goes to zero as the voltage on the drain of
the output device moves towards ground (VDD).
The second portion of the lab required us to
measure the current through both an NMOS and PMOS transistor using Vbiasn and Vbiasp from our BMR
circuit. Through analysis of the simulations and experimental results we should
see a constant increase in the current past the breakthrough voltage point.
Both MOSFETS will be biased similarly, so we should also observe that we have
similar current values.
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Schematic |
Simulation |
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The simulation confirms what we expected. Both
the nmos and pmos mirrors
have similar current slopes along with a similar breakthrough voltage at around
1.8V.
Experimental Data:
Our experimental values also reflect the results
we receive in the simulations. Our margin of error appears to be 1.2uA, which
is pretty good considering the amount of current is relatively tiny. We also
found at this experiment that it was better to increase the body size of our M2
transistor by placing 4 transistors in parallel. We then redid the experiments
up to this point and were able to obtain results closer to our simulations.
Part
3: Measuring current through gate-drain connected transistors
Using these current mirrors drive two gate-drain
connected transistors
o
For the first experiment use the NMOS current mirror to drive two
PMOS gate-drain connected devices.
·
Use the voltages on the gate-drain connection of the two devices
to bias a cascode current mirror (characterize this
mirror as before)
o
For the second experiment switch, that is, use the PMOS current
mirror to drive two NMOS gate-drain connected devices.
·
Again, use these two voltages to bias an NMOS cascode
current mirror then characterize.
Similarly to Part 2, we will be
biasing a cascoded, gate-drain connected branch of
transistors with our BMR circuit. This should produce similar results in the
plotting of the drain current. We observed that the breakthrough voltage is
increased in both cases. This may be a result of the voltage needing to be
higher as there are multiple voltage drops across the biased transistor branch.
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Schematic |
Simulation |
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Experimental results:
It can be observed that the experimental results
follow closely the graphs of the simulated results. Overall, this was
interesting to observe the effects of biasing a circuit using a BMR circuit. We
were able to demonstrate a couple different cases of biasing and how their
drain currents are affected.
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