Lab 8 - ECE 420L
e-mail:mcdonc4@unlv.nevada.edu
In this lab you will characterize the transistors in the CD4007 (not
the CD4007UB chip)
and generate SPICE Level=1 models. Assume that the MOSFETs will be used in the
design of circuits powered by a single +5 V power supply. In other words, don't
characterize the devices at higher than +5 V voltages or lower than ground
potential.
This lab will include:
1.
Part 1: NMOS Analysis
2.
Part 2: PMOS Analysis
3.
Part 3: Inverter Analysis
In this lab you will characterize the transistors
in the CD4007 and generate SPICE Level=1 models.
Assume that the MOSFETs will be used in the design of circuits powered by a
single +5 V power supply. In other words, don't characterize the devices at
higher than +5 V voltages or lower than ground potential.
Experimentally generate, for the NMOS device, plots of:
1. ID v. VGS (0 < VGS < 3 V)
with VDS = 3 V
2. ID v. VDS (0 < VDS < 5 V)
for VGS varying from 1 to 5 V in 1 V steps, and
3. ID v. VGS (0 < VGS < 5 V)
with VDS = 5 V for VSB varying from 0 to 3 V in 1 V steps.
·
Note that for this
last one, if VSS (NMOS body) is ground (again, the Body, VB, is grounded)
then the source voltage will be varied from 0 to 3 V in 1 V steps to realize
VSB ( = VS - VB = VS) varying from 0 to 3 V in 1 V steps. At the same
time VGS will be varied from 0 to 3 V (when VS = 0), 1 to 4 V (when VS = 1 V),
2 to 5 V (when VS = 2 V), and 3 to 5 V (when VS = 3 V). In other words, as
VS is increased by 1 V the VGS has to shift up by 1 V
as well.
·
Assuming that the
length of the NMOS is 5 um and its width is 500 um calculate
the oxide thickness if Cox (= C'ox*W*L) =
5 pF.
·
From this measured
data create a Level = 1 MOSFET model with (only) parameters: VTO, GAMMA, KP,
LAMBDA, and TOX.
·
Compare the
experimentally measured data above (the 3 plots) to LTspice-generated
data (again, 3 plots) and adjust your model accordingly to get better matching.
·
Repeat the above steps
for the PMOS device where VDS, VGS, and VSB are replaced with VSD, VSG, and VBS
respectively.
Part 1: NMOS Analysis
This lab requires us to generate a model level 1 LTSpice model in conjunction with our analyzed results. The
data will be displayed after showing the hand calculations we used to generate
the spice model, however the data was required to perform the calculations
prior to deriving them by hand.
We plotted our measurements in Microsoft Excel. Our spreadsheet
can be viewed at: https://drive.google.com/open?id=1vXBAn_xwIdDc5t4td4yAvB7waMy_GxGq
The figure below is the pin list / schematic for the CMOS ic.
We used the NMOS from pins 6, 7, and 8. In order to measure the
current of this NMOS we connected an ammeter in series from the drain the of
NMOS.
Hand Calculations:
Using these calculations, I created the following LTSpice model:
This model will be use in all the simulations in the following experiments.
Experiment 1:
1. ID v. VGS (0 < VGS < 3 V)
with VDS = 3 V
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Schematic |
Simulation |
Tested |
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Experiment 2:
2. ID v. VDS (0 < VDS < 5 V)
for VGS varying from 1 to 5 V in 1 V steps, and
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Schematic |
Simulation |
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Tested |
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Vgs
= 1 is too low to produce any results |
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Experiment 3:
3. ID v. VGS (0 < VGS < 5 V)
with VDS = 5 V for VSB varying from 0 to 3 V in 1 V steps.
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Schematic |
Tested |
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Tested |
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Part 2: PMOS Analysis
We will now repeat the same experiments for the PMOS circuit. We
will be using pins 1, 2, and 3 in the referenced figure below to perform this
analysis. Again, an ammeter will be applied in series to the drain to measure
the current flowing through the MOSFET.
Experiment 1:
1. ID v. VSG (0 < VSG < 3 V)
with VSD = 3 V
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Schematic |
Simulation |
Tested |
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Experiment 2:
2. ID v. VSD (0 < VSD < 5 V)
for VSG varying from 1 to 5 V in 1 V steps, and
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Schematic |
Simulation |
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Tested |
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Vsg
= 1 is too low to produce any results |
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Experiment 3:
3. ID v. VSG (0 < VSG < 5 V)
with VSD = 5 V for VBS varying from 0 to 3 V in 1 V steps.
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Schematic |
Simulation |
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Tested |
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Part 3: Inverter
Analysis
The final portion of the lab involved measuring the time delay of
the inverter. Utilizing the data sheet for the IC for the CD4007, we used
the following test circuit with the same input parameters to perform the measurement.
Under the typical conditions we should be receiving a propagation delay of 35ns.
After we obtained the output from the above push-pull amplifier, we can obtain the time delay using the figure below.
This is the output we received from inverter test circuit above.
We measured a time delay of 24ns
Simulations:
I
then simulated the following LTSpice circuits to observe
the performance of my spice model.
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Schematic |
Simulation |
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Time Delay = 29.5ns |
The previous parameter rendered a time delay of 29.5ns, so I
adjusted a parameter to see if we could get closer to the expected time delay
of 35ns. I adjusted Lambda in my spice model to be .0168 and received the
following result.
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Schematic |
Simulation |
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Time delay = 31ns |
The new time delay was measured at 31ns, which is slightly closer
to 35ns. I assume that if I decrease lambda further that I could get even
closer to the typical time delay