EE
420L Engineering Electronics II Lab - Lab 6
Single-stage transistor amplifiers
Authored by Your Name, Cody McDonald
E-mail: mcdonc4@unlv.nevada.edu
For best view of this lab report, view window in full-screen.
This lab will include:
0.
Prelab
Pre-lab work
- This
lab will utilize the ZVN3306A and ZVP3306A MOSFETs.
- Review
these datasheets and become familiar with these transistors.
- Verify
that the simulations seen in lab6_sims.zip reasonably
model the behavior of the transistors' ID v. VGS, ID v. VDS, and gm v. VGS
curves.
- Finally,
watch the video single_stage_amps and review single_stage_amps.pdf
Experiment 1: Source-follower
This is a two week
lab.
Source-followers operate with the
use of an input voltage that is connected to the gate and the output of the
source nodes. The input will be common to the drain of this transistor. The DC
operating point is calculated by using a voltage divider calculation. In this
case VDD will receive the voltage division. Vs will be ID times the 1k
resistor.
In
regard to the AC gain of the circuit, the
gain should be close to 1. We will calculate this by multiplying the id (AC
current) by the output resistance that we will calculate.
Simulate the operation of these amplifiers.
Gain simulation and testing:
|
Schematic |
Simulated |
Tested: NMOS |
PMOS |
|
|
NMOS gain: 0.999 PMOS gain: 0.9024 |
Gain: 1.127 |
Gain: 1.427 |
Hand calculate, and then verify your hand
calculations with experimentation and simulations, the gains and
the input and output resistances ensuring that your test signals are
at a high enough frequency that the caps have negligible impedance but not so
high that the gain is dropping off.
- If you build this circuit using electrolytic capacitors, assuming
the input AC signal swings around ground, put the "+" terminal
of the cap on the gate of the MOSFET. Please indicate, in your lab
report, that you understand why the capacitor is connected this way.
- The electrolytic capacitor is biased and must have
the positive terminal positioned towards the highest DC potential. In
this case, the electrolytic capacitor must be positioned towards the gate
voltage of 3.33v since the AC signal has a 0v DC offset.
Hand
calculations:
|
NMOS |
PMOS |
|
DC Analysis:
AC Analysis:
Gain:
Resistance:
|
DC Analysis:
AC Analysis:
Gain:
Resistance:
|
Here
are the values calculated above and inserted into a table:
|
Calculated Values |
NMOS |
PMOS |
|
Vin (DC OP) |
3.33V |
1.66V |
|
Vout (DC OP) |
1.3V |
4.61V |
|
GM |
18.3 mA/V |
10.6 mA/V |
|
Rin |
33.3k |
33.3k |
|
Rout |
52 |
86 |
In your lab report discuss, in your own
words, how to measure the input resistance.
We can measure input resistance by
inserting a resistor in series with the signal being input. The resistor being
inserted must be close to the input resistance that we calculated beforehand.
We would then measure the voltage drop over the resistor to determine the
current flowing through. We can then use ohm’s law to calculate the resistance
by dividing the voltage drop over the resistance. We should obtain the same
resistance that we anticipated in our calculations above.
Again, in your lab report discuss how to
measure the output resistance.
Similarly to determining the input resistance, we can
calculate the output resistance by attaching a resistor from the output of the
circuit to ground. The resistor must also be similar in value to the output
resistance we calculated beforehand. We will then take the voltage across the
resistor and divide it by the current flowing through the circuit. This will
result in a similar resistance as the one we just connected to the circuit.
For the following resistance
testing we will be measuring the voltage difference between the input/output
voltages and the voltage that proceeds the added resistor. This will create a 2
to 1 voltage divider and result in a voltage that is half of the input/output
voltage.
Resistance simulation and testing
|
Rin: Schematics |
Simulated (NMOS-top, PMOS-bottom) |
Tested: NMOS |
PMOS |
|
|
|
|
|
|
Rout: Schematics |
Simulated (NMOS-top, PMOS-bottom) |
Tested: NMOS |
PMOS |
|
|
|
|
|
Experiment 2: Common-source
Below are two common-source amplifiers. Discuss
the operation of these amplifiers in your lab report including both DC and
AC operation.
This amplifier takes a voltage
input through the gate and will output a voltage through the drain. Similar to the source-follower, the output signal will be
common to the source of the transistor. The DC operating point is calculated
the same way as the source-follower as it will be VDD in a 3 to 2 voltage
divider as it will show 3.33V. The NMOS drain voltage is found by subtracting
VDD by the voltage across the resistor, and the PMOS drain voltage will be
calculated by multiplying ID by the drain resistor.
Hand calculate the gains and the input/output
resistances. Again compare your hand calculations to
simulation and experimental results.
Hand
Calculations:
|
NMOS |
PMOS |
|
Constants
AC Analysis:
Gain:
Resistances:
|
Constants
AC Analysis:
Gain:
Resistances:
|
Here
are the values calculated above and inserted into a table:
|
Calculated Values |
NMOS |
PMOS |
|
Vin (DC OP) |
3.33V |
1.66V |
|
Vout (DC OP) |
3.7V |
0.39V |
|
GM |
18.3 mA/V |
10.6 mA/V |
|
Rin |
33.3k |
33.3k |
|
Rout |
1k |
1k |
Gain
Simulations and Measurements:
|
Schematic |
Simulated |
Tested: NMOS |
PMOS |
|
|
NMOS gain = -6.81 PMOS gain = -5.4 |
Gain = -4.708 |
Gain = -1.655 |
Resistance
Simulations and Testing:
|
Rin: Schematic |
Simulated |
Tested: NMOS |
PMOS |
|
|
|
|
|
|
Rout: Schematic |
Simulated |
Tested: NMOS |
PMOS |
|
|
|
|
|
How does the source resistance, Rsn or Rsp, influence the gain.
Increasing
Rsn of Rsp will decrease the
gain of the circuit. This is due to their inverse relationship to gain. This
can be verified by observing the equation we calculated for gain above. We’ve
increased Rsn in the above circuit and measured the
output below:
We
can see that the overall gain is small than the gain observed with Rsn at 100 ohms.
Experiment 3: Common-Gate
Below are two common-gate amplifiers. Discuss
the operation of these amplifiers in your lab report including both DC and
AC operation.
The
common-gate amplifier topology has an input on the source and will output
through the drain. Like the other topologies we’ve observed thus far, the input
signal and output signal will be common to the gate of the transistor in the
NMOS and PMOS branches. The DC operating
point is also a results of voltage division of VDD and will be 3.33V in our
experiment. The drain voltage is found by subtracting VDD by the voltage drop
across the drain resistor. Our drain voltage will be 3.7 and 0.39 respectively
for the NMOS and PMOS branches
Hand calculate the gains and the input/output
resistances.
Hand
Calculations:
|
NMOS |
PMOS |
|
Constants
AC Analysis:
Gain:
Resistances:
|
Constants
AC Analysis:
Gain:
Resistances:
|
Here
are the values calculated above and inserted into a table:
|
Calculated Values |
NMOS |
PMOS |
|
Vin (DC OP) |
3.33V |
1.66V |
|
Vout (DC OP) |
3.7V |
0.39V |
|
GM |
18.3 mA/V |
10.6 mA/V |
|
Rin |
152.9 |
186.2 |
|
Rout |
1k |
1k |
How does the source resistance, Rsn or Rsp, influence the gain.
An increase in source resistance
will result in a decrease in gain. This is because the two values are inversely
related as discovered in the above calculations.
Again compare your hand calculations to
simulation and experimental results.
Gain
Simulations and Testing:
|
Schematic |
Simulated |
Tested: NMOS |
PMOS |
|
|
NMOS gain = 6.81 PMOS gain = 4.9 |
Gain = 4.205 |
Gain = 1.4 |
Resistance Simulations and Testing:
|
Rin: Schematic |
Simulated |
Tested: NMOS |
PMOS |
|
|
|
|
|
|
Rout: Schematic |
Simulated |
Tested: NMOS |
PMOS |
|
|
|
|
|
Experiment 4: Push-Pull amplifier
Below is a push-pull amplifier. Discuss the
operation of this amplifier in your lab report including both DC and AC
operation.
The push-pull amplifier is a unique
amplifier topology as it utilizes both an NMOS and PMOS MOSFET. The input
enters through the gates of both MOSFETS and the output exits through the
drains of the MOSFETS. The gain of this amplifier produces an inverse gain, so
the output signal should be 180 degrees out of phase of the input.
Hand calculate the gain of this amplifier.
Hand
Calculations:
|
Push-Pull Amp |
|
Constants:
AC Analysis:
100k Gain:
510k Gain:
|
Do you expect this amplifier to be good at
sourcing/sinking current? Why or why not?
This amplifier will be especially
good at sinking and sourcing current since it contains both an NMOS and a PMOS.
If either the NMOS or PMOS is off the other transistor will be on. In either
case the circuit will be able to drive current through the circuit.
What happens to the gain if the 100k resistor
is replaced with a 510k resistor? Why?
This will result in an increase in
gain since we determined in the above calculation that a direct increase in
resistance will create a direct gain in the circuit.
Again compare your hand calculations to
simulation and experimental results.
|
Schematic |
Simulated |
100k Resistance |
510K Resistance |
|
|
Gain: 2850 |
Gain: 1200 We used an input of 1mv |
Gain:2280 We used an input of 1mv |
