EE 420L Engineering Electronics II Lab

Lab 9 - Design of a Beta–Multiplier Reference (BMR) using the CD4007 CMOS transistor array

 


Francisco Mata Carlos

 email: matacarl@unlv.nevada.edu

 4/24/19

 

 

Pre-lab:

  1. This lab will use the level=1 MOSFET model created in lab 8 and, again, the MOSFETs in the CD4007.pdf CMOS transistor array.
  2. Design and simulate the operation of a BMR that biases the NMOS devices so that they have a gm of 20 uA/V 
    1. Use a simple (big) resistor to VDD for the start-up circuit (explain how the addition of a resistor ensures start-up). 

                                                              i.      When the BMR is operating the current in the big resistor should be much smaller than the current flowing in each branch of the BMR 

  1. Write-up, similar to a homework assignment, your design calculations and simulation results.
  2. Ensure that you show the following in what you turn in:
    1. Hand calculations
    2. Operation as VDD is swept from 0 to 10 V 

                                                              i.      Vbiasn should stabilize (be constant) after VDD hits a minimum value (estimate this value of VDD assuming VGS/VSG is a threshold voltage and VDS,sat/VSD,sat is zero).

                                                            ii.      Vbiasp should follow VDD after VDD hits a minimum value (show this in simulations)

    1. Unstable operation if too much capacitance is shunting the BMR's resistor (see bottom of page 630)
    2. Comments comparing the hand calculations with the simulation results 

 

Based on the characterization of the transistors in the CD4007 for LAB 8, the hand calculations were produced

 

Hand Calculations:

 

After varying this value in LtSpice in order to match the parameters, the value used for R2 was 33.2kΩ

 

Below is the beta-multiplier reference (BMR), which was designed during the prelab section

   

 

The plot on the left below show how the current coming from the 1GΩ resistor injects current into drain node of M1 (diode connected) and drives the gate voltage up until VGS goes beyond the threshold voltage, which turns on M1, and allows the current from the PMOS to follow through. The plot on the right shows again the current from the big resistor being injected into the drain node of M1, which turns on this device. Once this NMOS turns on and the system starts working properly, the current calculated follows through each branch and stays constant.

 

        

 

The plots below show a DC sweep of VDD and how the system behaves as VDD increases. Once VDD reaches the minimum value or the threshold voltage, the Vbiasn node stabilizes and Vbiasp starts to follow VDD.

 

 

Lab description:

The goal of this lab is to use the BMR that was designed in the pre-lab and use it to test NMOS and PMOS current mirrors, and gate-drain connected cascode current mirrors.

 

Lab requirements:

  1. Build your BMR design and characterize it as you did in the pre-lab (if you use two chips ensure that grounds and VDDs of both chips are tied together).
    1. You expect the BMR to become unstable if there is a large capacitance across the resistor, such as a scope probe (important), so care must be exercised 
  2. Use your BMR to bias, and thus create, a:
    1. NMOS current mirror 
    2. PMOS current mirror
  3. Measure how the current varies through each current mirror as the voltage across the mirror changes.
    1. Of course the current in the NMOS (PMOS) current mirror goes to zero as the voltage on the drain of the output device moves towards ground (VDD)
  4. Using these current mirrors drive two gate-drain connected transistors
    1. For the first experiment use the NMOS current mirror to drive two PMOS gate-drain connected devices. 

                                                              i.      Use the voltages on the gate-drain connection of the two devices to bias a cascode current mirror (characterize this mirror as before)

    1. For the second experiment switch, that is, use the PMOS current mirror to drive two NMOS gate-drain connected devices.

                                                              i.      Again, use these two voltages to bias an NMOS cascode current mirror then characterize.

 

 

The values that we used for this experiment are as follows:

R2 = 30.7MEG, for the startup resistor

R1 = 32.7k, for the BMR

NMOS current mirror

Ltspice simulation

Experimental results

 

 

 

Plotting IV curve using Keithley 2450 SourceMeter

 

 

Excel plot using data from Keithley 2450 sourcemeter

 

 

 

 

 

PMOS current mirror

Ltspice simulation

Experimental results

 

 

 

Plotting IV curve using Keithley 2450 SourceMeter

 

 

 

Excel plot using data from Keithley 2450 sourcemeter

 

 

 

 

 

NMOS current mirror driving two PMOS gate-drain connected devices

Ltspice simulation

Experimental results

 

 

 

Plotting IV curve using Keithley 2450 SourceMeter

 

 

Excel plot using data from Keithley 2450 sourcemeter

 

 

 

 

PMOS current mirror driving two NMOS gate-drain connected devices

Ltspice simulation

Experimental results

 

 

 

Plotting IV curve using Keithley 2450 SourceMeter

 

 

Excel plot using data from Keithley 2450 sourcemeter

 

 

 

 



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