Lab 8 – EE 420L
Buchaa2@unlv.nevada.edu
In
this lab you will characterize the transistors in the CD4007 (not
the CD4007UB
chip) and generate SPICE Level=1 models. Assume that the MOSFETs will be used
in the design of circuits powered by a single +5 V power supply. In other
words, don't characterize the devices at higher than +5 V voltages or lower
than ground potential.
- Experimentally
generate, for the NMOS device, plots of:
- ID
v. VGS (0 < VGS < 3 V) with VDS = 3 V
- ID
v. VDS (0 < VDS < 5 V) for VGS varying from 1 to 5 V in 1 V steps,
and
- ID
v. VGS (0 < VGS < 5 V) with VDS = 5 V for VSB varying from 0 to 3
V in 1 V steps.
- Note that for
this last one, if VSS (NMOS body) is ground (again, the Body, VB, is
grounded) then the source voltage will be varied from 0 to 3 V in 1 V
steps to realize VSB ( = VS - VB = VS) varying
from 0 to 3 V in 1 V steps. At the same time VGS will be varied from 0 to
3 V (when VS = 0), 1 to 4 V (when VS = 1 V), 2 to 5 V (when VS = 2
V), and 3 to 5 V (when VS = 3 V). In other words, as VS is increased
by 1 V the VGS has to shift up by 1 V as well
- Assuming that
the length of the NMOS is 5 um and its width is 500 um calculate
the oxide thickness if Cox (= C'ox*W*L) = 5 pF.
- From this
measured data create a Level = 1 MOSFET model with (only) parameters: VTO,
GAMMA, KP, LAMBDA, and TOX.
- Compare the
experimentally measured data above (the 3 plots) to LTspice-generated
data (again, 3 plots) and adjust your model accordingly to get better
matching.
- Experimentally,
similar to what is seen on the datasheet (AC test circuits seen on page 3
of the datasheet), measure the delay of an inverter using these devices
(remember the loading of the scope probe is around 15 pF and there is other stray capacitance, say another 10 pF).
- Using your
model simulate the delay of the inverter and compare to measured results.
Adjust your SPICE model to get better matching between the experimental
data and the measured data.
- Repeat the
above steps for the PMOS device where VDS, VGS, and VSB are replaced with
VSD, VSG, and VBS respectively.
The lab ran out of CD4007
so we used CD4007UB which is the same chip with a higher supply voltage range,
but a similar pin layout. This is the pin layout of the
NMOS ID v. VGS (0<VGS<3V) with VDS = 3V
To generate this plot we set the drain to be 3V. To measure the current through
the drain we attached a 1k resistor in between the drain and the voltage source
we. The source pin was grounded, and the gate was incremented from 0-3V in
steps in 0.2V. we then took our measurements and threw them into an excel sheet
This is our excel plot
NMOS ID v. VDS(0<VDS<5V) with VGS varying from 1 to 5V in 1V
steps.
To generate this plot the drain is swept from 0-5V. while the gate is being
swept from 1-5V in 1V increments and the source was grounded. This time we
decided to use the multimeter to measure the current instead of a resistor and
the Voltmeter.
These are our plots
NMOS ID v. VGS(0<VGS<5) with VDS = 5V for VSB varying from 0
to 3V in 1V steps.
To generate this plot We supplied the drain with a fixed 5V. The body is
grounded, and the source is swept from 0-3V in 1V increments. The gate will
also be swept from 0-3V when Vs=0V, then we increased the initial gate voltage
to 1V and swept from 1-4V with a Vs=1 and we did this all the way up till the
initial gate voltage was 3v swept to 5V and the Vs was 3V.
These are our plots
NMOS hand calculations
We then calculated VTO KPn LAMBDA Tox and GAMMA
|
VTO |
1.4V |
|
KP |
12.26uA |
|
LAMBDA |
0.0141V |
|
TOX |
51.74nm |
|
GAMMA |
0.02V |
|
ID |
1.57mA |
This is the NMOS model we made
NMOS device simulations:
ID v. VGS (0<VGS<3V) with VDS = 3V
The simulations and the spice sim are almost the
same and the
both share the same VTO
ID v. VDS(0<VDS<5V) with VGS varying from 1 to 5V in 1V steps.
GREEN: VGS = 1V BLUE: VGS
=2V RED: VGS =3V TEAL: VGS =
4V PURPLE: VGS = 5V
The spice sim and the experimental results saturate at similar values. At
VGS=3V you can see the sim saturates at 1.6mA and the experimental is aprox 1.57mA
3. ID v. VGS(0<VGS<5) with VDS = 5V for VSB varying from 0 to 3V in 1V
steps
GREEN: VSB =
0V BLUE: VSB = 1V RED: VSB =
2V TEAL: VSB = 3V
the simulations and the experimental results match.
PMOS ID v. VSG (0<VSG<3V) with VSD = 3V
To generate this plot, the source is set to 3V and the drain is grounded. We
then swept the gate from 0-3V.
This is the PMOS excel
plot of the first part
PMOS ID v. VSD(0<VSD<5V) with VSG varying from 1 to 5V in 1V
steps
This is the excel plots of the PMOS for the second
part the VGS should be flipped to be VSG. This is because we used the same
spread sheet for both PMOS and NMOS but we didn’t
change the labeling.
PMOS hand calculations
|
VTO |
-1.6V |
|
KP |
6.8uA |
|
LAMBDA |
0.069/V |
|
TOX |
51.74nm |
|
GAMMA |
0.22V |
|
ID |
0.87mA |
This is the PMOS Model we made in spice.
PMOS device simulations:
1. ID v. VSG(0<VSG<3V) with VSD = 3V
You can see that the threshold voltage does not
match the simulation and therefor our simulations results may not match.
2. ID v. VSD(0<VSD<5V) with VSG varying from 1 to 5V in 1V steps
PURPLE = 1VSG TEAL =
2VSG RED = 3VSG BLUE =
4VSG GREEN = 5VSG
The results in this sim match our experimental
results, but you can see as previously predicted that the threshold voltage is
too high because there should be some current when VSG is 2V.
Inverter
This is the
experimental results for the inverter.
The delay through this inverter is approximately
22nS.
This is the simulation for the inverter.
Vout =
4.00165ms Vin = 4.00149
Delay = 16nS
|
Experiment
Delay |
Simulations
Delay |
|
22nS |
16nS |