EE 420L
Engineering Electronics II Lab- Lab 8
Characterization of the CD4007 CMOS
Transistor Array
Prelab work:
- Review the datasheet for the CD4007.pdf CMOS transistor array.
- Ensure that you understand how the bodies of the NMOS
are tied to pin 7 (VSS, generally the lowest potential in the circuit, say
ground) and that the bodies of the PMOS are tied to pin 14 (VDD, generally
the highest potential in the circuit, say + 5V).
Post lab work:
In
this lab you will characterize the transistors in the CD4007 (not
the CD4007UB chip)
and generate SPICE Level=1 models. Assume that the MOSFETs will be used in the
design of circuits powered by a single +5 V power supply. In other words, don't
characterize the devices at higher than +5 V voltages or lower than ground
potential.
- Experimentally generate, for the NMOS device, plots
of:
1. ID v. VGS (0 < VGS < 3 V) with VDS = 3
V
2. ID v. VDS (0 < VDS < 5 V) for VGS varying
from 1 to 5 V in 1 V steps, and
3. ID v. VGS (0 < VGS < 5 V) with VDS = 5 V for
VSB varying from 0 to 3 V in 1 V steps.
- Note that for this last one, if VSS (NMOS body) is
ground (again, the Body, VB, is grounded) then the source voltage will be
varied from 0 to 3 V in 1 V steps to realize VSB ( = VS - VB = VS) varying
from 0 to 3 V in 1 V steps. At the same time VGS will be varied from 0 to
3 V (when VS = 0), 1 to 4 V (when VS = 1 V), 2 to 5 V (when VS = 2
V), and 3 to 5 V (when VS = 3 V). In other words, as VS is increased
by 1 V the VGS must shift up by 1 V as well.
- Assuming that the length of the NMOS is 5 um and its
width is 500 um calculate the oxide
thickness if Cox (= C'ox*W*L) = 5 pF.
- From this measured data create a Level = 1 MOSFET model
with (only) parameters: VTO, GAMMA, KP, LAMBDA, and TOX.
Calculations for Cox, VTO, GAMMA, KP, LAMBDA,
and TOX
NMOS CALCULATIONS
Looking at the ID vs.
VDS for VGS = 3V we saw that
From the data above and
the calculations below, we found that:
|
Vthn |
1.75V |
|
Gamma |
0.287V |
|
Kpn |
7.296uA |
|
Lambda |
0.0257/V |
|
Id |
565uA |
|
tox |
17.25nm |
We found the value of
IDSat and then found two points to take the slope. The equations below solve
for the parameters we need to make the models.
IDSat= 565uA
Slope = 
Lambda = 
Vthn = 1.75V
PMOS CALCULATIONS
Below is our PMOS graph from the source meter,
however, because of an issue with the equipment, the graph is skewed. We used
the points from the graph to make an excel graph in order to measure the PMOS
values.
From the measurements
above at VSG = 5V we found that:
|
Vthp |
1.7V |
|
Gamma |
0.287V |
|
Kpp |
4.4uA |
|
Lambda |
0.0317/V |
|
Id |
2.4mA |
|
tox |
17.25nm |
We found the value of
IDSat and then found two points to take the slope. The equations below solve
for the parameters we need to make the models.
Slope = 
Lambda = 
Vthp = 1.70 V
Spice
Models:
From the values above, we created spice models
to model our experimental values. The values did not create the exact same
graph we found experimentally, so we changed the values in the spice models
until they were idea. Changing each parameter changes the way the graph looks.
After much testing, these are the values we settled on.
NMOS EXPERIMENTAL
RESULTS
1. Plot ID v. VGS (0 <
VGS < 3 V) with VDS = 3 V
Below are the points captured by manually measuring the currents
using a power supply and a multimeter and then plotted on excel in a graph
showing the curve. The
current goes up to 0.006A in the points generated by the sourcemeter
and the current goes up to 660uA in LTSpice which is only 60uA off from the
source-meter sims.
2. ID v. VDS (0 < VDS
< 5 V) for VGS varying from 1 to 5 V in 1 V steps
VGS of 1V, 2V, 3V, left
to right respectively.
VGS of 4V, 5V
Above
are the graphs made by the sourcemeter and below are the points captured by the
sourcemeter’s software. To right is a graph made by combining all of the graphs
and the poinst made by the sourcemeter.
The LTSpice simulations are very close to the
graph made by the source-meter because of the alterations made in the Spice models.
3. ID v. VGS (0 < VGS
< 5 V) with VDS = 5 V for VSB varying from 0 to 3 V in 1 V steps.
These points below were
found using a powersupply and a multimeter and then
plotted using excel.
PMOS EXPERIMENTAL
RESULTS
1.
ID v. VSG (0 < VSG < 3 V) with VSD = 3 V
Below are the points
captured by manually measuring the currents using a power supply and a
multimeter and then plotted on excel in a graph showing the curve.
Comparing
the results in LTspice to those measured shows us that the values are very
close in Spice because of the alterations of the Spice models. They both reach
about 600/700uA.
2.
ID v. VSD (0 < VDS
< 5 V) for VGS varying from 1 to 5 V in 1 V steps
VSG = 1V, 2V, 3V
VSG = 4V, 5V
Above
are the graphs generated by the source meter and below is an excel graph
generated by the values made by the sourcemeter.
The
current in the experimental values go up to about 3mA and those in LTSpice are
very similar to the experimental ones.
3. ID v.
VSG (0 < VGS < 5 V) with VDS = 5 V for VSB varying from 0 to 3 V in 1 V
steps.
Below are the values
found using the multimeter and the power supply for the third experiment. The
values are put into an excel graph and then compared to the LTSpice values.
Above are the values in
a table and below are the individual IV curves.
Below are all the IV ccurves together. They rise to 0.0035A.
The current in the excel graph rise up to about 3.5mA and the
graph made by LTSpice is almost identical in this case.
INVERTER DELAY
Using your model simulate the delay of the inverter
and compare to measured results. Adjust your SPICE model to get better matching
between the experimental data and the measured data.
Below are the
experimental results of the inverter. In our experiment, we found the delay to
be about 28ns.
Based on the LTSpice simulation
we can see that the delay is about 26ns which is very close to the experimental
simulation of 28ns.
The LTSpice simulation matches
the experimental results very well.