Lab 9 - ECE 420L 

Authored by Stephanie Silic

silics@unlv.nevada.edu

April 19th, 2017

Lab Description

• Ensure that you show the following in what you turn in:
• Hand calculations
• Operation as VDD is swept from 0 to 10 V 
• Vbiasn should stabilize (be constant) after VDD hits a minimum value (estimate this value of VDD assuming VGS/VSG is a threshold voltage and VDS,sat/VSD,sat is zero).
• Vbiasp should follow VDD after VDD hits a minimum value (show this in simulations)
• Unstable operation if too much capacitance is shunting the BMR's resistor (see bottom of page 630)
• Comments comparing the hand calculations with the simulation results

Lab Report

The BMR circuit is the following:

         

After building this circuit with the CD4007 chips on the breadboard I measured the voltage at the gate of M3 (of the spice schematic) for Vbiasn, the gate of M2 for the Vbiasp voltage, and the voltage across the resistor to measure the current Iref. We expect Vbiasn to maintain a fairly constant value after the threshold voltage of 2V, though it will increase with VDD. We expect Vbiasp to increase linearly with VDD, and we expect Iref to be at least 1.1uA (based on the initial calculations above), again after the higher threshold voltage, around 2V.

Table and plots of experimental values from BMR circuit are shown below, followed by the simulations generated by the Spice models:

The BMR seems to be started up at nearly 3V VDD, and teh Iref simulation is a lot lower than the measured values (and expectations). Adjusting the KPn in the Spice model to a higher value gives us the following Iref:

The Spice models now as follows:

The NMOS and PMOS current mirrors:

To measure the current experimentally through the NMOS and PMOS devices in the current mirrors, an ammeter was placed in series with the devices, and the readings plotted versus VDD varying from 0 to 10V:

  

We expect, as we see in the above results, that the bias voltages will increase with increasing VDD. But the variation of the measured data seems to vary far too much; the simulations vary less, and I did not deem it necessary to try to match the simulations once more to the data this time. Either something is wrong in the circuit or how I measured the voltage, or the BMR is simply not that good. The BMR is not designed to be a stable reference with respect to VDD, so this is the reason accepted as to why the Vbiasn is increasing so linearly with VDD.

NMOS current mirror driving two gate-drain connected PMOS devices and a PMOS current mirror driving two gate-drain connected NMOS devices:

The NMOS driving two gate-drain connected PMOS devices gives a higher current in the mirror than just the NMOS mirror in the measured data. However, the simulation shows the more ideal situation, where the mirrored current with the PMOS divices added is still the same as the mirrored current with a single NMOS device. The threshold voltage has also increased by nearly a volt for the NMOS mirror and nearly two volts for the PMOS mirror, even in the simulations.

Conclusion:

Dealing with these transistors was more difficult than expected. When the results aren't what I expected, a lot of time was spent trying to troubleshoot the circuit, wondering if there was a mistake somewhere. The lessons learned from Lab 8, characterizing the MOSFETs, and this lab, creating a beta-multiplier reference have been a good introduction to real-world design, where the models don't always match the measurements, and the measurements sometimes don't match the calculations. All these things need to be balanced, and an iterative process performed: calculate, simulate, measure, and repeat. 

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