Project - ECE 420L Engineering Electronics II Lab
Authored
by Frank Sanchez,
sanchezf@unlv.nevada.edu
05/2/2017
Project - design a transimpedance amplifier (TIA) using either the ZVN3306A or ZVP3306A (or both) MOSFETs and as many resistors and capacitors as you need with a gain of 30k.
You should try to get as fast a design as possible driving a 10k load
with as large of output swing as possible. AC coupling input and output
is okay as long as your design can pass a 100 Hz input current. Your
report, in html, should detail your design considerations, and measured results showing the TIA's performance. Note
that this is the same project assigned last year so this year we will
have one more constraint, that is, your design can draw no more, under
quiescent conditions (no input signal), than 0.3 mA from a +9 V supply
voltage (quiescent power consumption is less than 2.7 mW for any power
supply you use). Your report is due at the beginning of lab on Wednesday, May 3. Access to your CMOSedu.com accounts will be removed at this time.
Design
The trans-impedance amplifier is a current to voltage converter that is used to amplify the current output.
The
push-pull topology gives me the ability to have a large gain that is
linearly dependent to the reference resistor for the topology.
| Schematic |
 |
Theoretical Calculations
I decided to choose a resistor gain value of about 53k-ohms to achieve high gain in my TIA.
Gain (Frequency)-LTspice
The gain frequency below gives me a clear view of what to expect for my experimental data, for my TIA.
Gain (Frequency)
In the simulations seen below:
- yellow indicates Output.
- Blue indicates Input
- Purple indicates Voltage after the first input resistor
- Red indciates the voltage drop between my 10k-ohm resistor.
I
was able to find my Gain in regards to this. Using the same equation I
used above, I was able to find my gain in regards to frequency.| 100Hz |  | Gain:
53k | 10kHz |  | Gain:
51.57k |
| 1kHz |  | Gain:
53.947k | 100kHz |  | Gain:
31.47k |
As you can see, the experimental data correlated decently with my LTspice simulation.
You can also see the speed for my TIA in accordance to gain.
It
is good to note that my Input current was calculated using the input
voltage being fed in versus the voltage drop after the input resistor.
The math function above gave me the ability to do that.
For example i would say, 96mV-26mV=76mV/10k=7.6uA. Gain would be 410mV/7.6uA=53.9k.
Output Swing
The output swing showed a 2.4 volt swing. I used a 9Volt VDD.
Simulation
Expeimental Results
The results below show you a clear idea where my output swing starts to cutoff from the bottom and top halves.
my cutoff was approximately 1.5V which is really close to my simulation.
| 1st Cuttoff | 2nd Cutoff |
 |  |
Power Dissipation
Power dissipation can be found by know the voltage drop in between the VDD and the pmos. Using no function generator.
Tranistor Potentials
By using a 15k resistor on my sources of my transistors. It let me achieve a dc current of 160uA; when fed with 9volts.
Using EQNs. for square-law equations.
Kpn=0.1233.
Kpp=0.145.
My Vgs=1.87volts.
My Vsg= 2.92volts.
Vs of nmos is (160uA*15k)=2.4volts.
The gate is Vgs+2.4v=4.27volts.
Vs of pmos is 4.27+2.92=7.1volts.
All calculations were very close to my experimental results seen below.
| Gate: | Source for PMOS: |
Source for NMOS: |
 |  |  |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Conclusion:
My
TIA design has upwards of 50k gain when it drives a 10k load at a 100Hz
signal. In order to limit my current supplied i chose a topology that
proved to be helpful in doing so. This lab taught me how to comprehend
that.
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