Lab9 - EE 420L 

Authored by Allan Pineda
pineda3@unlv.nevada.edu
April 19, 2017   
Lab Description:  Design of a Beta-Multiplier Reference (BMR) using the CD4007 CMOS transistor array.

Experiment 1:
    In this part of the experiment it is required to build the beta multiplier using the parameter obtain from the previous laboratory. However, a wrong chips CD4007UBE was accidentally used which led to the wrong result value of the parameter. A CD4007CN is the right chip needed for this experiment. To complete this experiment, CD4007CN was evaluated to deterimine its parameter so it can be used to this experiment. Below is the resulting parameter values for CD4007CN.

   
                                                CD4007CN Parameters                                                                                                            Hand Calculation

    A two different power supply was used in the transistor to deterine the parameter of the transistor. In finding the threshold voltage for an NMOS, a 5V power supply was connected to the gate of the transistor and another supply to the drain. The power supply from thedrain  is swept from 0V to 10V. Looking at the current of the transistor where the changes is happen during the swept, one can determine the threshold voltage of the transistor. The voltage from the drain when change is happen came out to be around 3.2. Thus the threshold voltage for the NMOS device is 1.2V. As for the PMOS, the same process used. However, a drain was swept from 0V to 10V rather than the gate of the transistor.Thus the threshold of the transistor is around 1.75V. A threshold voltage then can be use to determine the other parameter such KPn and KPp using squarelog equation. See above for hand calculation.

Simulation of the Used Parameter:

    
                                   Beta-Multiplier Schematic                                                                                      Vbiasp Waveform                                                                                   Vbiasp Waveform

    The above simulation shows the saturation stage of the Vbiasp and Vbiasn of the transistor. Increasing the voltage from 0 to 10 volt will make the transistor to saturate at a certain voltage level. In the case of Vbiasp the saturation point is at 2V due to the threshold voltage of 1.75. While the Vbiasn is at 2V and has a threshold voltage of 1.2V.


                             Current Flow to each side of the circuit
The current flow through each side above is slightly different from each other due to the different parameter.


    At this point of experiment, the beta-multipilier circuit was built to verify the results and compared to simulation results. A multi-meter was used along with a power supply to plot the result while varying the power supply from 0V to 10V. Table 1 are collected data from beta-muliplier circuit.
Table 1.
Voltage  (V)VbiaspVoltage (V)VbiasnVoltage (V)Current 
1V17.1mV0.5V0.27V1V0uA
2V536mV1.0V0.49V2V1.22uA
3V1.54V1.5V0.73V3V1.36uA
4V2.57V2.0V1.02V4V1.44uA
5V3.47V2.2V1.49V5V1.54uA
6V4.44V3.0V1.51V6V1.60uA
7V5.45V5.0V1.54V7V1.68uA
8V6.42V7.0V1.57V8V1.75uA
9V7.53V9.0V1.58V9V1.83uA
10V8.42V10.0V1.60V10V1.89uA
 

See Below for Graphical Representation of Table 1.
 
  The graph above shows how Vbiasp and Vbiasn changes with respect to VDD. Both of the bias voltage match the simulation above.
 

    Here, the current did not really matched the simulation obtained above. This is due to the parameter use in the simulation. The paramater of the actual CD4007 is slightly different from the simualtion because the paramater used was just estimated. A slight difference in paramaters can make a big change in the output current. Also, the 10MEG resistor has a current drop around 900nA which added to M1  transistor. Using a big resistor can reduce this problem.


Experiment 2:
The second experiment is to create a current mirror for NMOS and PMOS using the beta multiplier above. To do so, additional device needed to perform the experiment. Below is the circuit representation of NMOS and PMOS current mirror. Table 2 are collected data from beta-muliplier circuit.

Table 2. 
NMOSCurrentMirror
Voltage (V)1V2V3V4V5V6V7V8V9V10V
Current (uA)0uA0.9uA1.1uA1.5uA1.8uA2.0uA2.3uA2.7uA2.9uA3.4uA
PMOSCurrentMirror
Voltage (V)1V2V3V4V5V6V7V8V9V10V
Current (uA)0uA2.5uA3.0uA3.6uA4.1uA4.2uA4.9uA5.3uA5.9uA6.5uA

See Below for Graphical Representation of Table 2.
 
These graphs are the result from the experiment. Notice that the experiment value is different from the simulation result. This is due to the parameter used in the simulation as explain above. Comparing these result, at 10V the pmos current is approximately 6.5uA while in the simulation is about 1.0uA only. These means that the actual current is 6 times larger compare to simulated value. For NMOS the current at 10V is approximately 3.4uA while in the simulation is about 1.8uA which is half the number of the actual experiment. See below for comparison.

Simulation of the Used Parameter:
   
                                                    PMOS Current Mirror Schematic                                                                                       PMOS Current Mirror Waveform

   
                                                   NMOS Current Mirror Schematic                                                                                        NMOS Current Mirror Waveform

Experiment 3
For this experiment, it is required to use the current mirrors created above to drive two gate-drain connected device or cascode. Below is the schematic used for cascoding NMOS and PMOS device.

 
                                                                         NMOS Cascode Schematic                                                                                                                           NMOS Cascode Waveform

  
                                                       PMOS Cascode Schematic                                                                                                               PMOS Cascode Waveform      


Again, the obtain value from the experiment is different compare to simulation beacuse of the parameter used.
 
                                            NMOS Cascode Current
Table 3. The value from the table below was obtain from varying the vcas from 0V to 10V. Here a pmos was not obtain due to the circuit problem in the bread board.
NMOS-Cascode
Voltage1V2V3V4V5V6V7V8910V
Current6uA6uA6uA6.1uA6.2uA6.3uA6.3uA6.3uA6.3uA6.4uA
Voltage1V2V3V4V5V6V7V8V9V10V
Current0.1uA0.1uA0.1uA0.5uA0.61uA0.68uA0.76uA0.84uA0.92uA0.99uA

Conclusion:
    This laboratory experiment is about creating a current mirror using a beta multiplier. There are numerous error and challenges to the design process such as the parameter use in the simulation is different than that the acutal parameter of the chips. however, the experiment was achieved using the estimation and concept learned from the lecture class. In creating a current mirror, it is very important that the device must identical to each other. This means that the VGS's of the transistor used must be identical as well as the threshold voltage of the these devices otherwise current mirroring could be hard to achieve.