Lab8 - EE 420L 

Authored by Allan Pineda
pineda3@unlv.nevada.edu
February 15, 2017   
Lab Description: Characterization of the CD4007 CMOS transistor array


Pre-lab work:

Experiment 1

In this laboratory experiment, CD4007 transistor will be characterized and generate a spice level=1 models. The maximum level power will be use to characterize the transistor is +5V.

The first device to be characterize is the NMOS. The goal is to generate  ID vs VGS  plots from  0V to 3V with VDS of 3V,  ID vs VDS plot from 0V to 5V with VGS varying from 1V to 5V in 1V steps, and ID vs VGS from 0V to 5V with VDS = 5V from VSB varying from 0 to 3V in 1 V steps.See Figure below.

NMOS:

ID vs VGS  plots from  0V to 3V with VDS of 3V:
   
                               Waveform Varying VGS from 0V to 3V                                                Schematic Varying VGS from 0V to 3V


ID vs VDS plot from 0V to 5V with VGS varying from 1V to 5V in 1V steps:

       
                    NMOS Schematic                                                                                                       VGS = 1
     
                        Waveform VGS = 2                                                                                                                     Waveform VGS = 3
  
                             Waveform VGS = 4                                                                                                                Waveform VGS = 5

ID vs VGS from 0V to 5V with VDS = 5V from VSB varying from 0 to 3V in 1 V steps.See Figure below:

   

 

PMOS:
The second device to be characterize is the PMOS. The goal is to generate  ID vs VSG  plots from  0V to 3V with VSD of 3V,  ID vs VSD plot from 0V to 5V with VSG varying from 1V to 5V in 1V steps, and ID vs VSG from 0V to 5V with VSD = 5V from VBS varying from 0 to 3V in 1 V steps.See Figure below.

At this point of the experiment, a multi-meter was use to find all paramater of the PMOS device.

ID vs VSG  plots from  0V to 3V with VSD of 3V:

  
     




ID vs VSD plot from 0V to 5V with VSG varying from 1V to 5V in 1V steps:

   
                                                        Schematic                                                                                                                            Waveform Result


VARYING VSD
           

VARYING VSG
       
ID vs VSD; Varying VSG=1ID vs VSD; Varying VSG=2IDvs, VSD Varying VSD=3IDvs, VSD Varying VSD=4IDvs, VSD Varying VSD=5
VSD = 0;  ID=0VSD = 0;  ID=0VSD = 0; V= 0 ID=0VSD = 0; ID=0VSD = 0; ID=0
VSD = 1;  ID=1uVSD = 1;  ID=38.3uVSD = 1;  ID=72uVSD = 1;  ID=144uVSD = 1;  ID=290u
VSD = 1.7;  ID=50uVSD = 1.7;  ID=192.6uVSD = 1.7;  ID=450uVSD = 1.7;  ID=906uVSD = 1.7;  ID=1760u
VSD = 1.9;  ID=68uVSD = 1.9;  ID=251.6uVSD = 1.9;  ID=820uVSD = 1.9;  ID=1305uVSD = 1.9;  ID=2150u
VSD = 2.7;  ID=82uVSD = 2.7; ID=320.8uVSD = 2.7;  ID=1034uVSD = 2.7;  ID=1760uVSD = 2.7;  ID=3240u
VSD = 3.9;  ID=95uVSD = 3.9; ID=403.7uVSD = 3.9;  ID=1080uVSD = 3.9;  ID=2160uVSD = 3.9;  ID=5400u
VSD = 4.2; ID=105uVSD = 4.2; ID=435.7uVSD = 4.2;  ID=1200uVSD = 4.2;  ID=3241uVSD = 4.2;  ID=6480u
VSD = 4.2; ID=138uVSD = 5.0; ID=450uVSD = 5.0;  ID=1221uVSD = 5.0;  ID=3375uVSD = 5.0;  ID=6615u

ID vs VSD from 0V to 5V with VSG = 5V from VBS  varying from 0 to 3V in 1 V steps.See Figure below:

       

Above shows how to find the KP, VTO and current flowing in the circuit. In part of NMOS oscilloscope was used to generate ID vs VDS curve and estimate the current with respect to VDS. For PMOS, a combination of multimeter and oscilloscope was use to measure voltage and calculate to the current to get the KP, VTo and other parameters of the device to be able to simualte the data.

Experiment 2

This experiment focus on calculations using collected data from previous experiment. Here, one can calculate the parameter using the data from the experiment above.

Given: 
L = 5um, W = 500um, Cox = 5pF



Experiment 3

In this part of experiment, simulation done by using the parameter data obtain above.



NMOS:

  
                 NMOS Schematic                                                                              NMOS Waveform

  
       NMOS Schematic sweeping both VGS and VDS                                 NMOS Waveform sweeping both VGS and VDS

  
    NMOS Schematic sweeping both VGS and VSB                                           NMOS Waveform sweeping both VGS and VSB  

PMOS:

  
                                      PMOS Schematic                                                                                PMOS Waveform

  
                          PMOS Schematic sweeping both VSG and VSD                                                            PMOS Waveform sweeping both VSG and VSD 

  
                     PMOS Schematic sweeping both VSG and VBS                                                      PMOS Waveform sweeping both VSG and VBS  


Experiment 4

  
           From Data Sheet Schematic                                                Schematic Simulation
 
                                                 Push-Pull Waveform

Conclusion:
 Thus base on the data above, the estimated values use in experiment is verifed through LTSpice since the values are not too far from each otehr. This lab experiment is very useful for future reference. It shows how to create a level=1 Spice list. Using oscilloscope is very though compare to ammeter to measure current. Using voltmeter and ammeter will expedite the work but it require a more mathematical calcualtion.