Lab6 - EE 420L 

Authored by Allan Pineda
pineda3@unlv.nevada.edu
February 22, 2017   
Lab Description: Single-stage transistor amplifiers

This lab will utilize the ZVN3306A and ZVP3306A MOSFETs. 

Experiment_1:
    The first experiment is a common drain amplifier or sometimes called source follower. A source amplifier is typically use as a voltage buffer.It is conviniently use in a high input impedance application and a low output impedance. The input is both fed into the gate of the transistors  and their output is the source while their drain is common for both input and output.

LT-Spice Simulation:


                                                     Schematic for Common-Drain Amplifier                                                                                                                           Simulation Result for Common-Drain Amplifier


The shematic above shows the connection of a common drain amplifier as well as the experimental results. Notice that in the simulation result was subtracted to show the AC output signal.





                            Input Resistance Schematic                                                                                                                                Output Resistance Schematic

 
              Input Resistance Simulation Result                                                                                                                  Output Resistance Simulation Result


Here are the hand calculation result together with the laboratory result verifying all calaculation. A 10 kHz frequency was used to short all the capacitor during AC analysis and open in a DC analysis. The capacitor used are electrolytic with a 8.2uF value instead of 10uF due to unavailablility of 10uF capacitor. In connecting the capacitor to the circuit, one must connect the "+" terminal to the incoming higher voltage due to polarity safety which mean it may damage the insulating oxide and acts like a short circuit between the capacitor terminal that may cause the capacitor to over heated.



                                                    NMOS: Gain                                                                                          NMOS: Input Resistance                                                              NMOS: Output Resistance


                                                    PMOS: Gain                                                                                          PMOS: Input Resistance                                                              PMOS: Output Resistance

Here the gain can be calculated by dividing the output peak voltage and the input peak voltage reading shown above. The gain is almost close to gain of 1 which imply that the simulation and hand calculation was verified. On measuring the input and output resistance, a value obtain from hand calculation must be use in the board and implement it through parallel connection to get an output of  50% of the input. When the resistance values obtain from calculation match the total resistance of the common drain resistor, the resulting output must be 50% of the input or close to verified the result..


Hand Calculation: NMOS                                                                                                                                                                                        Hand Calculation: PMOS                                 

The hand calaculation above shows how to get the value for input and output resistance to use in the lab experiment. In order to verify the calculation, one must add the calculated value to the circuit board and connect it in parallel between the two resistor or simply build a voltage divider. If the resulting output voltage of the circuit comes up to be haft the value of input voltage, then the calculated resistance value is verified. One can also measure the actual DC voltage between the voltage divider through multimeter available in the lab. In NMOS, the DC voltage is 3.33V and for PMOS is 1.667Vas shown in hand calculation above.For input resistance the voltage divider formula is Vout=Rin/(Rin+R_picked)*Vin, if Rin=R_picked => Vout = R/2R*Vin => Vout=(1/2)*Vin. For output resitance is also the same as input resistance.

NMOSHand calculationsSimulationExperimentalPMOSHand CalculationsSimualtionsExperimental
Gain0.95V/V0.90V/V0.80Gain0.9170.91V/V0.8V/V
Input Resistance33k ohms33k ohms33k ohmsInput Resistance33k ohms33k ohms33k ohms
Output Resistance49.46 ohms 33kohms49.46 ohmsOutput Resistance86.24 ohms86.24 ohms86.24 ohms


Experiment_2:
    The second experiment is about understanding the common source ampilifier and the effect of Rsn and Rsp in the circuit. A common source amplifiers are widely use for amplifying the input voltage.The gain of this amplifier is determined by the transconductance and partly depended on the bias point of the circuit. A change in the gate voltage will cause a change in the drain current. The gain varies with the change in Rsn and Rsp or both. The Higher the Rsn and Rsp the lower the output gain. Below are the result of the simulation.

Here the DC voltage is subtracted in the simulation to show the AC output voltage and the gain for PMOS and NMOS circuit.
LT-Spice Simulation:
           
                                                      Schematic for Common-Source Amplifier                                                                                                                           Simulation Result for Common-Source Amplifier

Simulating the gain of the common source amplifier as shown above. The resulting gain is approximately -6V/V. See Hand Calculation below.


                    Input Resistance Schematic                                                                                                                                Output Resistance Schematic

 
              Input Resistance Simulation Result                                                                                                                  Output Resistance Simulation Result

Above are the resulting simulation from to verify the result of the experiment. The gain of the this amplifier is -7 for NMOS and -5 for PMOS. To verify the input and output resistance of the amplifier, one must do a voltage divider and measure the voltage in the node. if the output voltage is half of the input voltage, the input and ouput resistance is verified. See below for verification result.


   
                                                    NMOS: Gain                                                                                          NMOS: Input Resistance                                                              NMOS: Output Resistance

   
                                                    PMOS: Gain                                                                                          PMOS: Input Resistance                                                              PMOS: Output Resistance

Here are the hand calculation that shows how to calculate the gain, input and output resistance of NMOS and PMOS of the common-source amplifier as well as verifying all the simulation result. A 10 kHz frequency was used to short all the capacitor during AC analysis and open in a DC analysis. The capacitor used are electrolytic with a 8.2uF value instead of 10uF due to unavailablility of 10uF capacitor. In connecting the capacitor to the circuit, one must connect the "+" terminal to the incoming higher voltage due to polarity safety which mean it may damage the insulating oxide and acts like a short circuit between the capacitor terminal that may cause the capacitor to over heated.

 
The above calculation was use to estimate the correct input and output resistor to verify the result in the lab experiment. The same principle from experiment 1 was used to verify the result for common source amplifier. However, increasing Rsn and Rsp value will result in lower gain.


NMOSHand calculationsSimulationExperimentalPMOSHand CalculationsSimualtionsExperimental
Gain-7V/V-7V/V-5.34V/VGain-5V/V-6V/V-3.58V/V
Input Resistance33k ohms33k ohms33k ohmsInput Resistance33k ohms33k ohms33k ohms
Output Resistance1k ohms 1k ohms998 ohmsOutput Resistance1k ohms1k ohms998 ohms


Experiment_3

The third experiment is a common gate amplifiers. A common gate amplifier has a low input resistance and and a high output resistance which can result in a high voltage gain but a low current and power gain circuits. Its input signal is applied to the source and the output is  taken from the drain. The source resistance Rsn, Rsp are inversely proportional to the gain and thus cause the gain to increase when they these source resistance is decreases.

                                                      Schematic for Common-Gate Amplifier                                                                                                                           Simulation Result for Common-Gate Amplifier

                             
                    Input Resistance Schematic                                                                                                                                Output Resistance Schematic

    
              Input Resistance Simulation Result                                                                                                                                                                                              Output Resistance Simulation Result


                                                    NMOS: Gain                                                                                          NMOS: Input Resistance                                                              NMOS: Output Resistance


                                                    PMOS: Gain                                                                                          PMOS: Input Resistance                                                              PMOS: Output Resistance
Above are the resulting simulation from to verify the result of the experiment. The gain of the this amplifier is 6.5 for NMOS and 5 for PMOS. To verify the input and output resistance of the amplifier, one must do a voltage divider and measure the voltage in the node. if the output voltage is half of the input voltage, the input and ouput resistance is verified. See table below for more a brief summary result.


NMOSHand calculationsSimulationExperimentalPMOSHand CalculationsSimualtionsExperimental
Gain6.5V/V6V/V4.77V/VGain54.7V/V3.29V/V
Input Resistance153 ohms153k ohms33k ohmsInput Resistance183k ohms183k ohms33k ohms
Output Resistance1k ohms 1k ohms1k ohmsOutput Resistance1k ohms1k ohms1k ohms


Experiment_4
The last experiment was for testing a push-pull amplifier. A push-pull amplifier is design to have an output that can drive a current in two different direction through a load. It has a high efficiency and high output power than can be use for low distortion. These amplifier can be a good source of sinking current. It is a class AB amplifier since it can go in either direction . A class A amplifier consist of NMOS and PMOS that are both on when their input and output have the same potential. When the input of VDD is connected to circuit, the PMOS is off and NMOS pushes current into load, and if the input is 0V the NMOS is off and the PMOS pulls current from the load, this is class B. Thus the amplifier is a class AB since it can operate both ways. When the load resistance is change into 510k ohms, the gain will dramatically increase.



                                                        Push-Pull Gain                                                                                                 Input voltage

Note: Since the input voltage is too small, the oscilloscope cannot read the value so a multimeter was use to measure the input voltage. Having a 600mV output reading and input reading 218micro-volt, one can calculate the gain of push-pull transistor is about 2752.9 V/V which is really close the hand calculation result..
 
                                          
Push-PullHand calculationSimulationExperimental
Gain2.9k V/V2k V/V2752.9 V/V