Final Project: Design of a Band Gap Reference (BGR) using the CD4007 - ECE 420L 

Authored By: Joey Yurgelon

Email: yurgelon@unlv.nevada.edu

April 30th, 2015

• Students will characterize use the techniques described in class to characterize and build a BGR.

• Project - using as many diodes, resistors, and capacitors as needed, along with two CD4007 chips from the same production lot (see date code on the top of chip) to ensure current mirrors are possible, design and build a bandgap voltage reference (BGR). Your report, in html, should detail your design considerations, simulation results (using the models you generated in lab 8), and measured results showing the BGR's performance (how the reference voltage changes with VDD). It would be good, but it's not required, if you could also characterize the BGR performance with temperature. Your report is due at the end of lab on Friday, May 8. Access to your CMOSedu.com accounts will be removed at this time. 

• Voltage references are used in circuits to genterate a fixed voltage, typically Vref, that is as consistent as possible. While Vref may change due to sweeps in VDD, changes in temperature, or process variations, it is the designers job to create a circuit that either minimizes these inconsistencies or eliminatae them all together. This may be the general rule, but it is not absolute. There are times when an increase to Vref is needed as temperature is increased, or possible the other way around. If an increase to Vref to temperature is needed, we refer to it as proportional to absolute temperature (PTAT), and complementary to absolute temperature (CTAT) is if a decrease in Vref to temperature is needed. In our case, we are using a topology that uses the PTAT characteristic of a resistor and the CTAT characteristics of a parisitic diode to counteract eachother to provice as stable of a Vref as possible with changes in temperature. As we will see, a needed parameter L will be calculated so that we may design for a Vref that is unvarying to temperature.

Design Considerations:

• Our Band-Gap Reference (BGR) consists of two stages. The first stage replicates much that of a Beta-Multiplier Reference (BMR) as created in 'Lab 9'. The differences are noted in how the branches of the device end. In regards to the BMR, the branches either end by going to ground or by going to a resistor followed by ground. To alter this, we add a diode followed by ground in the first branch, and a resistor followed by a diode in the second branch. This design can be seen in Fig. 1 below. The second stage is simply a PMOS current source feeding current into another resistor and diode followed by ground. The first stage of this design creates a PTAT reference circuit that drives a current into a a resistor for a PTAT voltage drop and a diode for a CTAT voltage drop. One then can add these drops to calculate Vref in the design. Since we want to know how Vref changes with temperature, a derivative is needed, and it is taken with respect to temperature (T). Since the voltage-temperature change of VT and VD are known values at 0.085mV/C and -1.6mV/C, respectively, we can solve derive an expression for 'L'  by setting the derivative to zero which is a multiplier value for the resistor in the second stage. Further details on the derivation, and generated expressions, can be seen below in Fig. 1. 

• The design we chose to follow requires the user to chain various diodes together in the second and third branch of the circuit which is represented by the variable 'K'. By increasing the number of diodes, the designer is able to increase the 'ln K' in the derivation below and thus increase the Vref voltage to the value one wishes. We could of increased the widths of various MOSFETs in the first stage of the circuit, but that would require us to use more than two CD4007 chips which is outside the project guidelines. In our case, we decided to keep K at a  nominal value of '8' so that the math would work out easier. After picking a R1 resistor value of 70kOhm, we are able to solve for a multiplier L to determine the value of R2 at ~680kOhms. The value of R1 was chosen simply so that we would have an easier time checking that the circuit was functioning correctly within the limits of our equipment. 

• I discuss our variation in Vref for a change in VDD below in Simulated/Experimental Results. This variation, while not the best, can be improved if the user wishes. The first way to improve the variation of Vref with VDD change is to place an amplifier in between the BMR type structure with the output connected to Vbiasp and the input terminals to the drains of the NMOS transistors.  By doing so, the amplifier will constantly regulate the voltages at the terminals, and hold the current at a much more stable value. The second way to improve on the design would be to cascode the structure. This would increase the output resistance of the current sources and thus make the current vary less with changes in VDD. While both of these ideas may prove fruitful, we could not achieve those designs while using only two CD4007 chips.

Fig. 1 - Band-Gap Reference Hand Calculations

Simulated Results:

• We were able to obtain very close results to that of our LTSpice simulations that were developed in 'Lab 8' for the CD4007 MOSFET arrays. This document can be found here. We were able to sweep VDD and measure both the current (Iref) through the structure as well as the voltage at Vref. We did have to add a 'Lambda' value of 0.5 in our spice model to account for channel length modulation. This gives us a more realistic result. According to the plots below, we achieved a Vref increase of approximately 282 mV, and an Iref increase of 442 nA per 1V increase in VDD. Experimentally, it is very difficult to test the dependence of Iref and Vref with respect to temperature, but one can get an idea by the simulations below. 

Fig. 2 - Iref Variations to Temperature/VDD	Fig. 3 - Vref Variations to Temperature/VDD
Fig. 4 - Close Up of Iref Variations	Fig. 5 - Close Up of Vref Variations
Fig. 6 - LTSpice Circuit Schematic

• The built circuit can be seen below. We used base-collector PNP 2N4403 transistors to serve as the diodes in our circuit. The large 'Blue' resistor seen below in Fig. 7 acts as the start up circuit for our design by leaking very little current into the NMOS gates so that the circuit snaps into operation. Even though this is typically unnecessary due to external noise when working with discrete components, it was added for completeness. From our experimental plots listed below, we achieved an increase of Vref by approximately 220 mV, and Iref of 350 nA per 1 V increase of VDD.

Fig. 7 - Band-Gap Reference Build
Fig. 8 - Experimental Iref Variations to VDD	Fig. 9 - Experimental Vref Variations to VDD
VDD 0 1 2 3 4 6 7 8 9 10 11 12 13 14 15 Iref (uA) 0.00 0.00 0.65 1.00 1.35 2.00 2.40 2.80 3.20 3.60 4.10 4.60 5.20 5.70 6.40 Fig. 10 - Data Points for Fig. 7	VDD 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Vref (V) 0.00 0.00 0.82 1.07 1.28 1.50 1.79 1.96 2.21 2.49 2.78 3.08 3.40 3.76 4.15 4.58 Fig. 11 - Data Points for Fig. 8

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