EE 420L Engineering Electronics II Lab - Lab 8
Mario Valles

April, 17 2015

vallesm@unlv.nevada.edu



In this lab you will characterize the transistors in the CD4007 and generate SPICE Level=1 models. Assume that the MOSFETs will be used in the design of circuits powered by a single +5 V power supply. In other words, don't characterize the devices at higher than +5 V voltages or lower than ground potential.

NMOS
PMOS
http://cmosedu.com/jbaker/courses/ee420L/s15/students/vallesm/Lab%208/NMOS%20Changing%20VGS.JPG
http://cmosedu.com/jbaker/courses/ee420L/s15/students/vallesm/Lab%208/PMOS%20changing%20VSG.JPG
      • http://cmosedu.com/jbaker/courses/ee420L/s15/students/vallesm/Lab%208/VSB.JPG
http://cmosedu.com/jbaker/courses/ee420L/s15/students/vallesm/Lab%208/delaysim.JPG
CKTs used

 http://cmosedu.com/jbaker/courses/ee420L/s15/students/vallesm/Lab%208/sim%20ckt.JPG

http://cmosedu.com/jbaker/courses/ee420L/s15/students/vallesm/Lab%208/delaycktsim.JPG