EE 420L Engineering Electronics II Lab - Lab 9
Mario Valles

vallesm@unlv.nevada.edu

April 24, 2015

Design of a Beta-Multiplier Reference (BMR) using the CD4007 CMOS transistor array

• This lab will use the level=1 MOSFET model created in lab 8 and, again, the MOSFETs in the CD4007.pdf CMOS transistor array.

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• Build your BMR design and characterize it as you did in the pre-lab
• Having calculated on the prelab the gm value, we got a resistor of 50k for our K=4 NMOS transistor of the beta multiplier
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• The following characterization was obtained
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• We create current mirros:
• NMOS current mirror  is M3
• PMOS current mirror is  M9
• Measuring the current mirrors we got the following results

• NMOS	PMOS
  We saw that the current was a litte bit greater in the pmos than the nmos	The current was smaller than the Beta-M for .01uA-.1uA, which was realy close. However, this results were obtained after ground alls VSS and put to VDD all VDD (1) pins of the transistor

  
  
• Using these current mirrors we drove two gate-drain connected transistors

NMOS	PMOS

When we say cascode we dont mean it. What we mead is two gate drain connected transistors.
Also, we saw the the current were very similar to the one meaure in the mirrors without the g/d-c transistors. They only few hundreds of nanoamps different.

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