Lab 8 - ECE 420L
Authored
by Silvestre Solano,
Email: Solanos3@unlv.nevada.edu
4-17-2015
This lab will use the CD4007 transistor array.
Experimentally
generate, for the NMOS device, plots of:
- ID v. VGS (0 < VGS < 3 V) with VDS = 3
V
- ID v. VDS (0 < VDS < 5 V) for VGS varying
from 1 to 5 V in 1 V steps, and
- ID v. VGS (0 < VGS < 5 V) with VDS = 5 V
for
VSB varying from 0 to 3 V in 1 V steps.
The
following plots were generated with the use of Excel. The data used to
make this plots was created in lab by using a 1k resistor and measuring
the voltage across it. Then using Ohms law, I was able to calculate the
current. This took a lot longer than it should have.
| ID v. VGS (0 < VGS < 3 V) with VDS = 3
V | ID v. VDS (0 < VDS < 5 V) for VGS varying
from 1 to 5 V in 1 V steps | ID v. VGS (0 < VGS < 5 V) with VDS = 5 V
for
VSB varying from 0 to 3 V in 1 V steps |
 |  |  |
Assuming
that the length of the NMOS is 5 um and its width is 500
um calculate the oxide thickness if Cox (= C'ox*W*L) = 5 pF.
Using
the parameters Cox = 5 pF, W = 500 um, L = 5 um, e0 = 8.85*10^-18 F/um,
and er = 3.97 , tox (oxide thickness) is calculated as follows.
The oxide thickness (tox) is calculated to be about 17.6 mm.
From
this measured data create a Level = 1 MOSFET model with (only)
parameters: VTO, GAMMA, KP, and TOX.
From
the ID vs. VGS (VSB = 0), VTO is about 1 V. TOX = 17.6 mm. KP is
estimated by taking the data from the ID vs VDS (VGS varying) and using
the square law equations to solve for KP. Of course, only the part of
the graph that is clearly in saturation was used. After avaraging the
current in a given curve and using the square law equation, then
avaraging the result, KP is roughly 7 uA/V^2. GAMMA is determined by
assuming that Vfp is equal to VB and solving for GAMMA according to the
equation below. GAMMA was found to be about 2.15 V^0.5.
The final text file that models the NMOS is shown below.
Compare
the experimentally measured data above (the 3 plots) to
LTspice-generated data (again, 3 plots) and adjust your model
accordingly to get better matching.
The plots for the NMOS simulations are shown below.
| ID v. VGS (0 < VGS < 3 V) with VDS = 3
V | ID v. VDS (0 < VDS < 5 V) for VGS varying
from 1 to 5 V in 1 V steps | ID v. VGS (0 < VGS < 5 V) with VDS = 5 V
for
VSB varying from 0 to 3 V in 1 V steps |
 |  |  |
Repeat
the above steps for the PMOS device where VDS, VGS, and VSB are
replaced with VSD, VSG, and VBS respectively.
| ID v. VSG (0 < VSG < 3 V) with VSD = 3
V | ID v. VSD (0 < VSD < 5 V) for VSG varying
from 1 to 5 V in 1 V steps | |
 |  | |
TOX
is calculated the same way assuming W and L are unchanged from the
NMOS. TOX = 17.6 mm. From the above graphs, VTO is about 0.75 volts. KP
is estimated the same way the KP for the NMOS was. The KP is estimated
to be about 4 uA/V^2. Since I did not have enough time to do the
varying VBS part for the PMOS, I will estimate the GAMMA paramater to
be smaller than the NMOS. GAMMA is probably something like 1.23. The text file with the model parameters is shown below.
The following table shows the simulated PMOS graphs.
| ID v. VSG (0 < VSG < 3 V) with VSD = 3
V | ID v. VSD (0 < VSD < 5 V) for VSG varying
from 1 to 5 V in 1 V steps | |
 |  | |
Experimentally,
similar to what is seen on the datasheet (AC test circuits seen on page
3 of the datasheet), measure the delay of an inverter using these
devices (remember the loading of the scope probe is around 15 pF and
there is other stray capacitance, say another 10 pF).
Using the CD4007 chip, the following scope picture was taken for the inverter. The delay is apparently 23.1 nS.
The simulation is shown below.
As always, I will back up my work as shown below.
Return to the main Lab directory.