Lab 6 - ECE 420L 

Authored by Silvestre Solano,

Email: Solanos3@unlv.nevada.edu

3-20-2015

 

 

 

This lab will utilize the ZVN3306A and ZVP3306A MOSFETs.
 
Below are schematics for NMOS and PMOS source followers amplifiers (also known as common-drain amplifiers).
 

 
In your lab report discuss the operation of these circuits.
 
The above amplifiers are essentially the same, except of course one is built using a PMOS while the other is built using an NMOS. Their gains, which are calculated below, are approximately the same. As with all the amplifiers in this lab, the transistors are biased with the DC source VDD. Both amplifiers have a voltage divider that divides the DC inputs by 1/3. Therefore, both transistors have a Gate Voltage of 5/3= 1.67 Volts. The C1 and C2 capacitors are there to act as an open circuit to prevent the DC gate voltage to be shorted to ground while not causing a voltage drop for the AC Vin.
 
Simulate the operation of these amplifiers.
 
SchematicTransient analysisSPICE error log
 
In the above table, the gmn and gmp were determined from the simulations and are approximately gmn = 0.0183 and gmp = 0.0107.
 
Hand calculate, and then verify your hand calculations with experimentation and simulations, the gains and the input and output resistances ensuring that your test signals are at a high enough frequency that the caps have negligible impedance but not so high that the gain is dropping off.
 
Gain (NMOS)
 



 
Gain (PMOS)
 

 

 

 
Rin (For both NMOS and PMOS)


 
Rout (NMOS)

Rout (PMOS)

 
If you build this circuit using electrolitic capacitors, assuming the input AC signal swings around ground, put the "+" terminal of the cap on the gate of the MOSFET. Please indicate, in your lab report, that you understand why the capacitor is connected this way.
 
This is because the gate is at a higher DC potential than the AC input, which is essentially DC ground.
 
In your lab report discuss, in your own words, how to measure the input resistance.

 
To measure the input resistance, I put a 33k Ohm resistor in between the gate of the transistor and the 1uF capacitor. Then, I will measure the gate voltage with respect to ground. If the input resistance is indeed the calculated value of 33K Ohms,  then the measured voltage should be 1/2 of the input voltage. Essentially, I am creating a voltage divider with the 33k Ohm resistor and the Rin of the input. This works for both NMOS and PMOS By measuring the voltage across Rin, I will be able to determine Rin as follows:
 

 

 

 
To verify Rout, the procedure is very similar to the verification of Rin. For Rin, I put a 51 Ohm resistor in series with the output Voutn to a 10 uF capacitor that goes to ground. The 10 uF capacitor is there to act as an open circuit in DC in order to preserve the DC bias. Again, this is essentially a voltage divider. If the Rout is actually 51.8 Ohms, then the ouptut voltage should be half of the input voltage. This is shown below for the NMOS:
 

 

 

 
The calculation for PMOS Rout is the same except a 85.5 Ohm resistor is used.
 
Below are the results of the lab experiment.
 
Vout/Vin (Gain)RinRout
NMOS
NMOS calculationsVout/Vin = 186 mV / 208 mV = 0.89Vout/Vin = 98 mV / 216 mV = 0.45Vout/Vin = 116 mV / 208 mV = 0.56
PMOS
PMOS calculationsVout/Vin = 232 mV / 264 mV = 0.88Vout/Vin = 120 mV / 212 mV = 0.57Vout/Vin = 112 mV / 204 mV = 0.55
 
As seen in the above table, the experimental results suprisingly seem to match the hand calculations and simulations. Both the gain of the NMOS and PMOS amplifiers are both essentially 1 as expected and the experimental results for both Rin and Rout of both NMOS and PMOS are all very close to 1/2.

     

Below are two common-source amplifiers.

Discuss the operation of these amplifiers in your lab report including both DC and AC operation.

 

The operation of these amplifier is essentially the same as the common drain amplifier except that they have a higher gain due to the Rsn and Rsp resistors. Again, both transistors are biased with DC sources while they are analyzed using thier AC inputs. The capacitors are present to act as open circuits in DC and prevent messing up the DC biasing. Thier source is common to both inputs.

 

Hand calculate the gains and the input/output resistances.
 
Gain (NMOS)



 

 
Gain (PMOS)
 




 
Rin (NMOS and PMOS)


 
Rout (NMOS)

According to professor Baker, the resistance is so large for the transistor that the Rout is "for all intents and purposes" is only the resistance of R8 which is 1k Ohms. I assumed the same is true for the PMOS.

How does the source resistance, Rsn or Rsp, influence the gain.
 
Rsn and Rsp are very small compared to the 1k Ohm resistor in parallel with them. Thus, this makes the overall parallel resistance less than 100 Ohms, which makes the gain for both NMOS and PMOS amplifiers to be large due to the inverse relationship of the gain and Rsp/Rsn in parallel with the 1k Ohm resistor.
 
Again compare your hand calculations to simulation and experimental results.
 
Simulation
SchematicTransient AnalysisSpice error log

According to the above table, the gmn and gmp remain unchanged from the Common Drain amplifier. The simulations also seem to match the hand calculations for the gain as can be seen when comparing the output with the input, there is an approximate gain of 5 for the PMOS and a gain of 7 for the NMOS.
 
Experimental Results
 
Vout/Vin (Gain)RinRout
NMOS
NMOS calculationsVout/Vin = 1.16 V / 0.204 V = 5.69Vout/Vin = 296 mV / 560 mV = 0.53Vout/Vin = 280 mV / 580 mV = 0.48
PMOS
PMOS calculationsVout/Vin = 536 mV / 200 mV = 2.68Vout/Vin = 536 mV / 200 mV = 2.68Vout/Vin = 144 mV / 336 mV = 0.43
 
The procedure for how to determine Rout and Rin from measurements in lab is identical to the Common Drain amplifier previously discused. So, if the ratio of input to output is about 0.5, then the Rin and Rout closely match the hand calculations. For the NMOS gain, the experimental value and calculated value are off. They have about a 17 percent difference, but I thing it is okay. However, the gain for the PMOS is about half of what it should have been. These descrepencies are probably caused by slightly different gmn and gmp from the ones determined in the simulation.
 
Below are two common-gate amplifiers.
 

 
Discuss the operation of this amplifier in your lab report including both DC and AC operation.
 
The operation is the same as the Common Source amplifier except that the Vin is now on the Rsn and Rsp while the gates for both transistors are grounded. Because the gate is common to the inputs and outputs, this amplifier is called a Common Gate amplifier. Again, the DC component is there to bias the transistors and the capacitors are there in order to preserve correct DC biasing conditions such as preventing the DC gate voltage from being shorted to ground. The AC component is what is measured and analyzed in lab.
 
Hand calculate the gains and the input/output resistances.
 
In order to simplify the calculations, I will make the simplification that most of the current id will go through the Rsn or Rsp instead of the 1k Ohm resistor.
 
Gain (NMOS)




 
Gain (PMOS)
 



 
Rin (NMOS)

Rin (PMOS)

 
Rout (NMOS and PMOS)
Again, professor Baker said it was about 1K Ohms
 

How does the source resistance, Rsn or Rsp, influence the gain.
 
Again, the gain is inversely proportional to Rsn or Rsp, which would cause the gain to increase as Rsn or Rsp decrease. In this circuit, Rsn and Rsp are both small compared to the other resistors used.
 
Again compare your hand calculations to simulation and experimental results.
 
Simulation
 
SchematicTransient analysisSpice error log


Experimental resuls
Vout/Vin (Gain)RinRout (Input)Rout (Output)
NMOS
NMOS calculationsVout/Vin = 1.24 V / 0.280 V = 4.43Vout/Vin = 152 mV / 304 mV = 0.5Vout/Vin = 304 mV / 420 mV = 0.72 (note that Vin is the output without the 152 Ohm resistor and Vout is the output with the 152 Ohm resistor.)
PMOS
PMOS calculationsVout/Vin = 680 mV / 272 mV = 2.5Vout/Vin = 152 mV / 304 mV = 0.5Vout/Vin = 480 mV / 900 mV =  0.53 (note that Vin is the output without the 185 Ohm resistor and Vout is the output with the 185 Ohm resistor.)

For the NMOS amplifier, the gain is about 4.43, which is significantly lower than the calculated and simulated value of 6.47. For the PMOS amplifier, the gain is about 2.5, which is almost exactly half of what was calculated and simulated. As before, the PMOS is about half of its expected value and the NMOS gain is off. This could be due to a different number of reasons ranging from human error to different gm paramaters. I believe that it is likely the gm parameters that are different than those of the simulations. For the Rin and Rout, if the ratio of input to output is about 0.5, then the calculated value of the Rin and Routs are pretty accurate. For the Rout of both the NMOS and PMOS, I had to take into account that the gain was large from the Vout, and I had to measure the Vout when no resistor was attached (either the 152 or 185 Ohm resistor) in order to get and accurate input reading and then I added the resistor( either the 152 or 185 Ohm resistor) in order to get the output. Ther ratio of these two had to be close to 0.5 using the voltage divider technique previously described. As seen in the above table, the ratios are about 0.5. The NMOS is a little off and the PMOS is very closes. In my opinion, this strongly suggests that the calcluated values of Rin and Rout of both amplifiers are accurate.

Below is a push-pull amplifier.

 

Discuss the operation of this amplifier in your lab report including both DC and AC operation.
 
At a first glance, this amplifier is clearly an inverter with a 100k resistor connecting the input and outputs. It is this resistor that greatly influences the AC gain of this amplifier.  Apparently, if the R1 resistor is increased, the gain will also be increased. In other words, the gain is directly proportional to the value of the R1 resistor.
 
Hand calculate the gain of this amplifier.
 

 


=3940
 
Do you expect this amplifier to be good at sourcing/sinking current? Why or why not?
 
No, I do not believe it is good at sourcing or sinking current because of the large 100k restor which greatly limits the current that can be achieved.
 
What happens to the gain if the 100k resistor is replaced with a 510k resistor? Why?
 
The gain increases as is shown in the experimental results. However, I don't believe this was supposed to happen. What should have happened is that the 510k Ohm was large enough that the output would be saturated due to the ridiculously high gain. In other words, the output would swing to AC ground since the source of both transistors are at AC ground. The 510k Ohm resistor would almost be like an open circuit and the amplifier would act as a simple inverter, but for the AC analysis, the output would swing to ground.
 
Again compare your hand calculations to simulation and experimental results.
Note that the gain of this amplifier is large so the output may saturate at VDD and Ground. To avoid this saturation you can reduce the AC input voltage using a voltage divider.



Simulation
SchematicTransient analysisSpice error log

 Experimental Results
100k Ohm510k Ohm
Gain
Gain calculationVout/Vin = 472 mV / 10 mV = 47.2Vout/Vin = 1.20 V / 10 mV = 120
 
In the lab experiment, I used a voltage divider using a 1k Ohm resistor in series with a 9k Ohm resistor in order to divide the input voltage by 10. The input shown in the above scope pictures is the undivided input. Howver the gain is considerably less than what was calculated and simulated. I expected a gain of 4000, but the gain is clearly not even one tenth. I originally used a 1 mV input to get a 4 volt output, but that did not seem to work at all, so I tried the 10 mV input. It is possible that for the voltage divider the resistors were to large for a 1 mV output, which would explain the amplifiers failure to work properly. However, adding the 510 k Ohm resistor increased the gain which was unexpected as explained previously. It is likely that the gm parameters are much, much smaller than the simulated values of gmn = 18.8m and gmp = 20.6m.

  

As always, I will back up my stuff as shown below.

 


 

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