Project - ECE 420L 

Authored by Silvestre Solano,

Email: Solanos3@unlv.nevada.edu

5-8-2015

Project - using as many diodes, resistors, and capacitors as needed, along with two CD4007 chips from the same production lot (see date code on the top of chip) to ensure current mirrors are possible, design and build a bandgap voltage reference (BGR). Your report, in html, should detail your design considerations, simulation results (using the models you generated in lab 8), and measured results showing the BGR's performance (how the reference voltage changes with VDD). It would be good, but it's not required, if you could also characterize the BGR performance with temperature. Your report is due at the end of lab on Friday, May 8. Access to your CMOSedu.com accounts will be removed at this time.

 
The lab project seems fairly simple. The goal is to build a bandgap reference, which is a circuit that attempts to ouput a voltage, often called Vref, that remains constant with variations in the supply voltage VDD and temperature. The bandgap built in lab is shown in the following LTspice schematic below.
 


I had originally built a completely cascoded bandgap as shown in Figure 23.27 on page 765 of professor Baker's CMOS book. However, that particular circuit only started to have an appropriate Vref value at about VDD = 6 Volts. This was not good since we are supposed to have the circuit working at at least VDD = 5. Taking professor Baker's advice, I removed the cascoded NMOS MOSFETS, which left only two NMOS MOSFETS as shown in the above schematic. The PMOS were left in a cascode structure. For this design, we arbitrarily choose to have 8 diodes in parallel for a K = 8.

The bandgap reference circuit is esentially a combination of a PTAT (Proportional to Absolute Temperature) circuit, which is a circuit where Vref increases with temperature, and CTAT (Complementary to Absolute Temperature) circuit in which Vref decreases with increasing temperature. They are put together so that the increases and decreases balance each other in Vref as temperature increases. This is essentially how Vref stays relatively constant as temperature changes.
 
In order to obtain the value for L, which determines the resistor size in the PMOS current mirror on the right, the following derivation must be performed.
 

 
From the above derivation, it can be seen that L is equal to about 9, assuming n = 1. Since I arbitrarily choose R1 to be 1k Ohms, R2 had to be nine times the size, or 9k Ohms.
 
I then proceded to build this circuit in lab using two breadboards. Why did I use two breadboards? I honestly can't remember. The completed product required 4 CD4007 chips. Although the CMOSedu website stated that only two CD4007 chips could be used, I choose to ignore it because professor Baker said I could use more than two. The finished circuit is shown below. Clearly, there are more than 4 chips in the picture, but only 4 were actually connected. The rest are from several failed attmpts at the bandgap circuit.
 

  

Since we did not have a reliable way of causing a change in temperature, the effects of temperature variance ond Vref could not be measured. However, we were able to sweep VDD from 0  to 15 volts and the results are shown in the table below.

 

VDD (V)Vref (V)
00
10
20
30.1843
40.6828
51.2878
61.3258
71.3449
81.3583
91.3727
101.3857
111.3988
121.4086
131.4203
141.4328
151.4476
 
The graphical representation of the above data is shown below
  

 
The only real flaw in the bandgap is that it only reaches its full Vref value at about VDD = 5 Volts. It would have been better if it reached its full value at atleast VDD = 3 Volts and remain mostly unchanged after VDD increases. However, the total change of Vref from 5 to 15 volts is about 0.1598 Volts.
 
The simulation results for the LTspice schematic shown at the begining of this report are shown below. The simulation shows Vref changing as VDD changes and has multiple curves representing Vref and different temperatures.
 

 
Comparing the simulation results and experimental results, it can be seen that the simulated Vref reaches its full value when VDD reaches about 4 volts. Then, the simulation shows that Vref does not change much between the values of 1.2 and 1.4 Volts. However, the simulation result does not completely match the experimental results other than the general shape of the graph. The reason for the differences between the simulatied and experimental results lie in the models constructed in lab 8. The are not very accurate to say the least. The differences could also be attributed to human error, such as improper wiring of the circuit and so forth.
 
And as always, I will back up my stuff as shown below.
 

 

 

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