Lab 9 - EE 420L 

Authored by Shada Sharif,

sharifs@unlv.nevada.edu

24 April 2015

Pre-lab work:

• This lab will use the level=1 MOSFET model created in lab 8 and, again, the MOSFETs in the CD4007.pdf CMOS transistor array.
• Design and simulate the operation of a BMR that biases the NMOS devices so that they have a g_m of 20 uA/V 
• Use a simple (big) resistor to VDD for the start-up circuit (explain how the addition of a resistor ensures start-up). 
• When the BMR is operating the current in the big resistor should be much smaller than the current flowing in each branch of the BMR 
  
• Write-up, similar to a homework assignment, your design calculations and simulation results. (This will count as the pre-lab quiz.)
• Ensure that you show the following in what you turn in:
• Hand calculations
• Operation as VDD is swept from 0 to 10 V 
• Vbiasn should stabilize (be constant) after VDD hits a minimum value (estimate this value of VDD assuming VGS/VSG is a threshold voltage and VDS,sat/VSD,sat is zero).
• Vbiasp should follow VDD after VDD hits a minimum value (show this in simulations)
• Unstable operation if too much capacitance is shunting the BMR's resistor (see bottom of page 630)
• Comments comparing the hand calculations with the simulation results

• The lab was about designing our own beta-multiplier and making a current mirror using the level=1 mosfet model created from previous lab.

• Build your BMR design and characterize it as you did in the pre-lab
• You expect the BMR to become unstable if there is a large capacitance across the resistor, such as a scope probe (important), so care must be exercised 
  
• Use your BMR to bias, and thus create, a:
• NMOS current mirror 
• PMOS current mirror
• Measure how the current varies through each current mirror as the voltage across the mirror changes.
• Of course the current in the NMOS (PMOS) current mirror goes to zero as the voltage on the drain of the output device moves towards ground (VDD)
• Using these current mirrors drive two gate-drain connected transistors
• For the first experiment use the NMOS current mirror to drive two PMOS gate-drain connected devices. 
• Use the voltages on the gate-drain connection of the two devices to bias a cascode current mirror (characterize this mirror as before)
• For the second experiment switch, that is, use the PMOS current mirror to drive two NMOS gate-drain connected devices.
• Again, use these two voltages to bias an NMOS cascode current mirror then characterize.

• Shown above the parameters that were found from Lab #8 for the CD4007 MOSFET.
• The first step of the lab was utilizing the the beta multiplier designed from the prelab. The BMR used for this lab is as shown below:

• For a start-up circuit the big resistor 33k ohms was connected to VDD, and it work similar to how the start-up does by slowing the current down until the current mirror reach the desired state.
• Moreover for M2 K of them were used in parallel so that we can ensure there is some voltage left for the resistor R1.

• As shown above, we can see how Vbiasn increases and reaches a steady point at around 2V and that is due to the threshold voltage for the CD4007, and Vbiasp reaches 2V and keeps increasing with increasing VDD just as was described in the pre-lab requirements.
• Moreover, the current produced in both branches of the BMR are shown above with varying VDD. At around 5V which is the VDD used, the current should be around 200nA.
• After using LTspice to make sure the design work, we built the BMR on the breadboard and tested its Vbiasn, Vbiasp, and the current while varying VDD. To do so a multimeter was used along with a power supply. The plot for these are shown below from the data collected:

• From the data collected above, we can see that Vbiasn and Vbiasp match the LTspice simulations very good. As for the current it is in microamp while simulations indicated the current should be in the nanoamp range. This could be due to the fact that the parameters used to calculate the current in the simulations are not exact with what they really are for the CD4007, or the matching was not done well since there was not many ICs found in the lab.

• Second part of the lab was using the working BMR to bias a NMOS and PMOS so that we can create a current mirror. As shown below, the following was done to mirror current using the Vbiasn, and Vbiasp voltage. Each was done simultaneously and not together. 

•   After doing so for each MOS separately, we measured the current in each while varying VDD again from 0~10V. The result is as the following:

• As expected for the NMOS it increases a little and reached a constant state which is due to Vbiasn being constant after 2V, and since Vbiasn is connected directly to the gate of the NMOS and it is basically its VGS then the current behaves the same meaning it also stays constant when Vbiasn is constant.
• For the PMOS we saw before that Vbiasp keeps increasing and the same argument again is present here, which is that the current changes correspondingly as Vbiasp. 
• In this experiment we had a separate VDD for the MOSFETS and varied Vbiasn and Vbiasp separately to make sure the biasing of the mirrors are correct.

• In this experiment if we wanted to use both NMOS and PMOS mirror at the same time then the following should be made:

• But in order to do so we needed another chip but since we already were using 4 chips for the project we decided to use the mirrors separately.
• This would have to be done because in a current mirror the current is the same on both branches but in the beta-multiplier we have K times the current on one branch so we will need a different stage.

Experiment #3

• Lastly, we used the current mirrors created from experiment #2 to drive a two gate-drain connected transistors. The schematic of what was done is shown below:

• The two drain gate connected MOSFETS create a cascode current mirror or also known as the Miller killer. This is done so we can get a high output resistance and this will ensure having a more ideal case close to an ideal current source with infinite output resistance.

• From the plots above we can see that the PMOS cascode is what we want it to be with a very high output resistance and we see the current between the range of 4V to 9V almost constant.
• The NMOS cascode did not work properly as seen above showing almost a linear increase with increasing VDD, which is not what is desired.

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