Lab 8 - EE 420L 

Authored by Shada Sharif,

sharifs@unlv.nevada.edu

17 April 2015

Pre-lab work:

• Review the datasheet for the CD4007.pdf CMOS transistor array.
• Know that NMOS bodies are tied to pin 7 (VSS, generally the lowest potential in the circuit, say ground) 
• Bodies of the PMOS are tied to pin 14 (VDD, generally the highest potential in the circuit, say + 5V). 

• This lab was about characterizing the NMOS and PMOS transistor CD4007, and through the parameters found we create a Level=1 LTspice models that can be used in simulations.

• NMOS and PMOS wave forms that were found experimentally.
• calculations and answers for the parameters VTO, GAMMA, KPn/p, and TOX.
• LTspice simulations using the Level=1 model.
• scope pictures of the inverter delay tested.
• The delay of the inverted tested in simulations. 

In this lab we characterize the transistors in the CD4007 and generate SPICE Level=1 models. Assuming that the MOSFETs will be used in the design of circuits powered by a single +5 V power supply.

• One method was using the scope XY feature and for the voltage that was varied we used a function generator to generate a sawtooth wave by taking a triangle wave and changing the duty cycle. Doing so enabled us to have a sawtooth wave varied in the range desired. Since using the scope we cant measure the current on the XY, we used a small resistor 100 ohms and measured the voltage across it (this was the Y-axis) and to get the current we simply divide the voltage at a chosen point by the resistance value. The X-axis here was the varied voltage.
• The other method was the simpler one that is to use a power supply and vary the voltage manually and testing the current directly with a ammeter that is placed in series with the terminal desired (for the NMOS the ammeter was placed on the drain, while the PMOS the ammeter was placed on the source).
  

1. ID v. VGS (0 < VGS < 3 V) with VDS = 3 V 

2. ID v. VDS (0 < VDS < 5 V) for VGS varying from 1 to 5 V in 1 V step

 

In this experiment when VGS=0V the NMOS showed zero ID since with a 0V the mosfet VGS is smaller than Vth which causes the device to be shutoff.
For the other plots shown above, the VDS was varied from 0V to 3V which can be seen on the X-axis to be 6 blocks with a 500mV division so 3V. To find the current at a certain point, take for example when VGS=5V and when VDS=1V we see that the point there on the Y-axis is 200mV divided by 100 which is the resistor value, we get 2mA that is 2000µA.

Note: VDS should have been varied from 0 to 5V but we did 0 to 3V, we did not notice this until we finished the lab and we not able to redo the waves. Basically if we varied VDS from 0 to 5V the wave would have been the exact same but with more flat line (which is the VGS value) shown at the right side.

3. ID v. VGS (0 < VGS < 5 V) with VDS = 5 V for VSB varying from 0 to 3 V in 1 V steps.

In this part of experiment we used a different lab (350) that had function generators that would only go up to %80 duty cycle since they were old. Due to this, the sawtooth wave was not perfect and error was introduced to the circuit which can be seen in the waves above. Changing the potential of the body affects the threshold voltage. As Vsb increases that is by increasing the potential of the source, the threshold voltage increases and causes the current to start to decrease because in the range the VGS is varied the device will not reach the threshold voltage required to start conducting current.

Now plots for the PMOS device:

1. ID v. VSG (0 < VSG < 3 V) with VSD = 3 V 

 

 
This time the ammeter and a power supply was used to measure the current while varying VSG.

2. ID v. VSD (0 < VSD < 5 V) for VSG varying from 1 to 5 V in 1 V step

The plots above do not look perfect since at the beginning more point were taking in smaller increments due the huge jump in current at 1V so if the measurements were taken at 1V increment the plots would look more like they should when VDS is varied in a mosfet.

3. ID v. VSG (0 < VSG < 5 V) with VSD = 5 V for VBS varying from 0 to 3 V in 1 V steps.

Again here we see the same idea as in the NMOS where varying the VBS changes the threshold voltage, but here it can be seen better where the blue plot is when VBS=0V we see that we get the most amount of current and as VBS is increasing line in VBS=3V the yellow cure is seen to have the smallest amount of current.

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Experiment #2

This experiment consisted mostly of calculations using informations/data from the plots generated in experiment #1.

Given:

• L=5um, W=500um, Cox=5pF

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Experiment #3

Using the parameters from experiment #2 in CD4007_models

We notice that the NMOS waves match the experimental results while the PMOS is a little off so we fix it by changing the parameters accordingly.

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Experiment #4

Using the circuit shown below, we measured the delay.

So from the scope, using the measure feature we measure the delay to be 50 ns.

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Experiment #5

Simulation of experiment #4 shown below

Conclusion:

This las taught us how to create a level=1 Spice list which is something very useful for the future. In this experiment it would have been more accurate and easier to use an ammeter to find the waves instead of using a scope.

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