EE 420L - Lab 9

Design of a Beta-Multiplier Reference (BMR) using the CD4007 CMOS transistor array

Authored by Nicholas Moya

April 23rd, 2015

moyan1@unlv.nevada.edu

The purpose of this lab is to build a beta-multiplier reference circuit using the CD4007 chip. The BMR circuit is then used to bias a cascode current mirror which in turn is connected to a load.

 Using 4 chips, the following schematic is build:

Although we didn't include it in our schematic, we use a big resistor connected between VDD and Vbiasn as our start up circuit. This is done because the big resistance, effectively increases Vbias node to 5V so that it can start up the circuit as VDD sweeps. Also note that we connect two NMOS's in parallel to effectively create a single NMOS with double the width. This is of course our beta multiplier. Using the parameters we measured last lab, we conduct the following calculations of Vbias voltages, Vcascode voltages, Vds sat and the (theoretical) max load we could connect to the circuit and have the circuit supply the same amount of current as without. Also note that we use the cascode bias circuit for better matching as matching is hard enough to accomplish in real world chips.

  .MODEL N_level1 NMOS LEVEL = 1
+ TOX    = 1.13E-14
+ VTO    = 0.8
+ GAMMA  = 1
+ KP     = 9.38E-6
*
.MODEL P_level1 PMOS LEVEL = 1
+ TOX    = 1.13E-14
+ VTO    = 0.8
+ GAMMA  = 1
+ KP     = 4.8E-6

 Calculations:

 Next, we sweep VDD and test how well our voltages respond. Note that Vr is the voltage across the 20k Ohm resistor and I is the current through it. Below, we include Excel plots of each parameter swept from VDD = 0 to VDD = 10.

Vbiasp

Vbiasn

Current in the Current Mirror

Vbias3

 Vbias4

 Current in NMOS Cascode Current Mirror

 Vbias1

 Vbias2

 Current in PMOS Cascode Current Mirror

Notice how our circuit responds fairly linearly for our parameters: Vbiasn = 20mV /VDD, Vbiasp = 1v/VDD, Vr = 5mV/VDD, and I = 0.20uA/VDD. We can attribute this to our relatively good matching given our chip avalibility. 

We now compare the simulated results to our actual values measured in lab. We record our measured values and plot them using Excel.

 Conclusion

 Our simulation results are very different from our experimental sketches. This can be attributed to the fact that it is hard to peform proper matching with transistor chips even if they are from the same production date. That being said, our Vbiasn is actually pretty good as it achieves as relatively linear result, only rising 0.2V from VDD = 2 to VDD = 10. Our simulated results could have been more accurate to our experimental data if we had used the proper length, width, and lamda parameters. As such, our length and width are arbitrarily choosen and lambda isn't included. Doing so could increase the accuracy of our siluated data and could therefore be used to better model our parameters and create more accurate experimental results.