Project - EE 420L
Authored
by Hongzhong Li,
Today's
date: 05/08/2015
Email:lih12@unlv.nevada.edu
Project description
using
as many diodes, resistors, and capacitors as needed, along with two
CD4007 chips from the same production lot (see date code on the top of
chip) to ensure current mirrors are possible, design and build a
bandgap voltage reference (BGR). Your report, in html, should detail
your design considerations, simulation results (using the models you
generated in lab 8), and measured results showing the BGR's performance (how the reference voltage changes with VDD). It
would be good, but it's not required, if you could also characterize
the BGR performance with temperature. Your report is due at the end of lab on Friday, May 8. Access to your CMOSedu.com accounts will be removed at this time.
Design Consideration
To
design a BGR, we first refer to the Beta-Multiplier Reference (BMR) we
created in Lab 9. We want the voltage drop across the resistor to be
constant and therefore does not vary with the supply voltage. We
will need to create a BMR in combine with diodes and resistors so that
the temperature and voltage does not vary at the same time. In this
case, we want to combine a PTAT(proportional to absolute temperature)
and a CTAT(complementary to absolute temperature) design into our BMR.
We design our bandgap voltage reference using diodes connected in parallel in each branch to stablize Vref. By increasing the
number diodes, K we can calculate the resistor values and the Length
required for resistors so that Vref won't vary with temperature.
In
the process of creating this op-amp, the first major design constraint
was the limitation of only two CD4007 chips. If one looks at the CD4007 datasheet,
each chip has 3 pairs of NMOS and PMOS transistors. Each N/P pair is
gate connected, which means that while each chip has 6 transistors (12
total), only 3 per chip (6 total) can be used if independent gates are
desired.
Due
to this limiation, we cannot cascode our circuit and therefore there is
variation in Vref for a change in VDD. By cascoding the circuit, we can
increase the output resistance of the current sources and thus make
Vref not change with VDD as much.
Schematic
Hand Calculations
We
choose K to be 8 for the simplicity of calculation, and the biased
current to be 1uA. The branch on the most right can increase the output
resistance of the circuit such that the voltage drop across the
resistor in seres with the K diodes does not varied with temperature.
Simulation
As
we mentioned before, the curve is not flat due to the circuit is not
cascode structured and therefore the output resistance is not high
enough for Vref to not vary with VDD.
Experimental Result
| VDD | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | | | |
|
|
| Vref (V) | 0.00 | 0.00 | 0.85 | 1.17 | 1.28 | 1.50 | 1.79 | 1.92 | 2.21 | 2.49 | 2.78 | | | | | |
Conclusion
As
we mentioned before, by cascoding the circuit we will be able to
achieve very high output resistance and therefore have a Vref that do
not vary with VDD and temperature. But due to limitations we can only
construct a circuit that vary with VDD for about 0.25-0.35V per 1 V of
VDD.
This concludes the project, all work has been back up and sent to email.
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