Lab 9 - EE 420L
Authored by Hongzhong Li,
Today's date:04/24/2015
Email: lih12@unlv.nevada.edu
Lab description
Pre-lab work
- This lab will use the level=1 MOSFET model created in lab 8 and, again, the MOSFETs in the CD4007.pdf CMOS transistor array.
- Design and simulate the operation of a BMR that biases the NMOS devices so that they have a gm of 20 uA/V
- Use a simple (big) resistor to VDD for the start-up circuit (explain how the addition of a resistor ensures start-up).
- When
the BMR is operating the current in the big resistor should be much
smaller than the current flowing in each branch of the BMR
- Write-up,
similar to a homework assignment, your design calculations and
simulation results. (This will count as the pre-lab quiz.)
- Ensure that you show the following in what you turn in:
- Hand calculations
- Operation as VDD is swept from 0 to 10 V
- Vbiasn
should stabilize (be constant) after VDD hits a minimum value (estimate
this value of VDD assuming VGS/VSG is a threshold voltage and
VDS,sat/VSD,sat is zero).
- Vbiasp should follow VDD after VDD hits a minimum value (show this in simulations)
- Unstable operation if too much capacitance is shunting the BMR's resistor (see bottom of page 630)
- Comments comparing the hand calculations with the simulation results
- Build your BMR design and characterize it as you did in the pre-lab
- You
expect the BMR to become unstable if there is a large capacitance
across the resistor, such as a scope probe (important), so care must be
exercised
LT-Spice Simulation
| Operation as VDD is swept from 0 to 10 V |
| |
Experimental Result
In order to prevent the circuit from going unstable we used a decoupling capcitor across the resistor as seen below:
Without Capactior(unstable) | With Capacitor(stable) |
| |
We measured Vbiasn and Vbiasp as VDD is swept from 0 to 10 V and input the data into excel to generate the following plot:
- Use your BMR to bias, and thus create, a:
- NMOS current mirror
- PMOS current mirror
- Measure how the current varies through each current mirror as the voltage across the mirror changes.
- Of
course the current in the NMOS (PMOS) current mirror goes to zero as
the voltage on the drain of the output device moves towards ground (VDD)
LT-Spice Simulation
Experimental Result
NMOS current mirror
PMOS current mirror
- Using these current mirrors drive two gate-drain connected transistors
- For the first experiment use the NMOS current mirror to drive two PMOS gate-drain connected devices.
- Use
the voltages on the gate-drain connection of the two devices to bias a
cascode current mirror (characterize this mirror as before)
- For the second experiment switch, that is, use the PMOS current mirror to drive two NMOS gate-drain connected devices.
- Again, use these two voltages to bias an NMOS cascode current mirror then characterize.
Experimental Result
NMOS Cascode
PMOS Cascode
We
realized that the experiemental data does not match exactly as our Hand
Calculations/Simulatons. This is because we assume there is perfect
matching and the circuit always operate in stable condition. However,
in practical these circuits will affect by other factors as well
therefore the result does not match exactly.
This concludes the Lab 9, all work has been back up and emailed.
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