Lab 9 - EE 420L 

Authored by Hongzhong Li,

Today's date:04/24/2015

Email: lih12@unlv.nevada.edu

 

Lab description

 

Pre-lab work


   
    LT-Spice Simulation
 
Operation as VDD is swept from 0 to 10 V

 Experimental Result
 
In order to prevent the circuit from going unstable we used a decoupling capcitor across the resistor as seen below:
 
Without Capactior(unstable)With Capacitor(stable)
 
  We measured Vbiasn and Vbiasp as VDD is swept from 0 to 10 V and input the data into excel to generate the following plot:
 

 
       LT-Spice Simulation

 
 Experimental Result
 
NMOS current mirror 

 
PMOS current mirror

  

 Experimental Result

 NMOS Cascode

 

  

PMOS Cascode

 

 

We realized that the experiemental data does not match exactly as our Hand Calculations/Simulatons. This is because we assume there is perfect matching and the circuit always operate in stable condition. However, in practical these circuits will affect by other factors as well therefore the result does not match exactly.

 

This concludes the Lab 9, all work has been back up and emailed.

 

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