Lab 8 - EE 420L 

Authored by Hongzhong Li,

Today's date : 04/17/2015

Lab description

 In this lab you will characterize the transistors in the CD4007 and generate SPICE Level=1 models. Assume that the MOSFETs will be used in the design of circuits powered by a single +5 V power supply. In other words, don't characterize the devices at higher than +5 V voltages or lower than ground potential.

• Experimentally generate, for the NMOS device, plots of: 

1. ID v. VGS (0 < VGS < 3 V) with VDS = 3 V 
2. ID v. VDS (0 < VDS < 5 V) for VGS varying from 1 to 5 V in 1 V steps, and 
3. ID v. VGS (0 < VGS < 5 V) with VDS = 5 V for VSB varying from 0 to 3 V in 1 V steps. 

• Note that for this last one, if VSS (NMOS body) is ground (again, the Body, VB, is grounded) then the source voltage will be varied from 0 to 3 V in 1 V steps to realize VSB ( = VS - VB = VS) varying from 0 to 3 V in 1 V steps. At the same time VGS will be varied from 0 to 3 V (when VS = 0), 1 to 4 V (when VS = 1 V), 2 to 5 V (when VS = 2 V), and 3 to 5 V (when VS = 3 V). In other words, as VS is increased by 1 V the VGS has to shift up by 1 V as well.
• Assuming that the length of the NMOS is 5 um and its width is 500 um calculate the oxide thickness if Cox (= C'ox*W*L) = 5 pF.
• From this measured data create a Level = 1 MOSFET model with (only) parameters: VTO, GAMMA, KP, and TOX.
• Compare the experimentally measured data above (the 3 plots) to LTspice-generated data (again, 3 plots) and adjust your model accordingly to get better matching.
• Experimentally, similar to what is seen on the datasheet (AC test circuits seen on page 3 of the datasheet), measure the delay of an inverter using these devices (remember the loading of the scope probe is around 15 pF and there is other stray capacitance, say another 10 pF).
• Using your model simulate the delay of the inverter and compare to measured results. Adjust your SPICE model to get better matching between the experimental data and the measured data.
• Repeat the above steps for the PMOS device where VDS, VGS, and VSB are replaced with VSD, VSG, and VBS respectively.

Ensure that your html lab report includes your name, the date, and your email address at the beginning of the report (the top of the webpage).
When finished backup your work.

From this measured data, VTO, GAMMA, KP, and TOX can be obtained.
Assume L=5u, W=500u, and Cox=5p.
 
Tox= eo*er/C'ox = 8.85E-18*3.75 / (5p/(5u*500u)) = 175.7E-10 for both NMOS and PMOS
VTO: Based on the first ID vs VGS (VSG) results, the threshold voltage for NMOS and PMOS is 1V and 1.5V respectively.
KP = 2*ID / VDSSAT^2. KPn = 600E-6 and KPp = 1000E-6.
GAMMA: Gamma was approximated by taking the change in threshold voltage divided by the change in body voltage. Body voltage has a high effect on NMOS, while it has a negligible one on the PMOS. NMOS =0.7 PMOS = 0.2.

The following SPICE Level=1 model assumes these values: CD4007_models.txt

LT SPICE Simulations to verify the experimental plots above:

 ID v. VGS (0 < VGS < 3 V) with VDS = 3 V

ID v. VDS (0 < VDS < 5 V) for VGS varying from 1 to 5 V in 1 V steps

ID v. VGS (0 < VGS < 5 V) with VDS = 5 V for VSB varying from 0 to 3 V in 1 V steps.   

PMOS

ID v. VSG (0 < VSG < 3 V) with VSD = 3 V 

ID v. VSD (0 < VSD < 5 V) for VSG varying from 1 to 5 V in 1 V steps

Experimental Data

 NMOS and PMOS plots:

• Experimentally, similar to what is seen on the datasheet (AC test circuits seen on page 3 of the datasheet), measure the delay of an inverter using these devices (remember the loading of the scope probe is around 15 pF and there is other stray capacitance, say another 10 pF).

Time delay = 23.1 ns
 

Simulations

This concludes lab8, all the work has been back up and uploaded to my email.

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