Lab 8 - ECE 420L
Authored
by Nicholas Banas,
Banasn1@unlv.nevada.edu
3/19/15
This lab characterized the CD4007 transistor array.
ID v. VGS (0 < VGS < 3 V) with VDS = 3 V
The first set of measurements were for varying Vgs with a fixed Vds.
For all measurements we used a 100 ohm sampling resistor to
measure the current.
Model matching is fairly close, Vthn measured is slightly lower in this plot and current is therefor higher at 3V Vgs.
ID v. VDS (0 < VDS < 5 V) for VGS varying from 1 to 5 V in 1 V steps
The fist sim is in pA, so it should look like the strait line in the measured results.
Matching is again fairly good for the saturation voltage. However, the
saturation current is significantly lower in the first two sims and
catches up in the third.
ID v. VGS (0 < VGS < 5 V) with VDS = 5 V for VSB varying from 0 to 3 V in 1 V steps.
For some reason the Vsb measurements did not sim well at all. I received two messages in the SPICE error log:
Model "n_4007": Oxide thickness thinner than recommended for a level 1 MOSFET.
Instance "m1": Length shorter than recommended for a level 1 MOSFET.
This may have had something to do with the problems.
Again, only the first two sims are even close.
The SPICE Model
To calculate the SPICE model we assumed a length of 5um a width of 500um and a Cox of 5pf.
C'ox = 5pf/(5um*500um) = 2fF/um^2
tox = 3.9*8.85aF/um / 2fF/um^2 = 172.6 A
KPn = 580 cm^2/Vs * 2fF/um^2 = 116 uA/V^2
GAMMA = Sqrt(2*1.6*10^-19*11.7*8.85aF/um*10^16)/2fF/um^2 = 0.288V^.5
I
found a much more thorough level 1 SPICE model that has the NMOS widths
at 20u instead of 500, this was invaluable in making the sims come even
close to matching.
Here is the test circuit used for the sim results.
AC test circuits
We also tested the switching results for an inverter made from the
CD4007. The yellow line is the function gen input and the blue is
the inverter output.
Measured Results: tPHL ~ 24.5 ns
From the datasheet:
Our measured tPHL was actually under the the typical for VDD of 5v.
