Homework assignments and Project Information for ECE 5/418 Memory Circuit Design, Spring 2010
Homework guidelines are found here.
HW#12 – due
Wednesday, April 21, A19.4 and repeat Ex. 19.4 with an input frequency of 25
MHz, no divider in the feedback path, and a modified VCO (re-design the VCO so
that it has good characteristics when the DPLL input and output are both 25
MHz)
HW#11 – due
Wednesday, April 14, A19.1-A19.3
HW#10 – due
Monday, April 5, A18.5, also simulate the operation of a 4-phase charge pump
using the CMOSedu 50 nm models that can generate 4 V and supply > 100 uA of
current. Using SPICE generated clock signals is okay. Characterize your design
by plotting output voltage versus load current.
HW#9 – due
Wednesday, March 24, A18.1-A18.2, A18.4
HW#8 – due
Wednesday, March 10, A17.2-A17.4
HW#7 – due
Monday, March 1, A17.1
HW#6 – due
Monday, February 22, use Electric and LTspice to
demonstrate the operation (writing and sensing) of a 2 by 2 SRAM array. Make
sure that your understanding of equilibration, sensing, and transistor sizing
considerations are clear in your solution.
HW#5 – due
Wednesday, February 17, discuss, in detail, the
(likely) layout of the arrays (blocks, sub-array size, page size, etc.) for the
Micron
1Gb DDR3 SDRAM. Make sure you provide details like number of I/O lines
below the array and how you know this (page size and array size). Be very clear
and simple (no magic).
HW#4 – due
Monday, February 8, A16.8 and use simulations and the sense-amp seen in Fig.
16.32 to show: 1) kickback noise, 2) memory (modify the sense-amp to show the
problems), excess current consumption, sensitivity to mismatch and how it
limits minimum sensing voltage (show how a mismatch can make the sense amp
repeatedly make the same decision for small input signals). Your discussions
and simulations should be simple and clear illustrating the concerns and
problems.
HW#3 – due
Wednesday, February 3, using Electric and LTspice make schematics for a 2 by 2
DRAM array (use 25 fF for the mbit capacitance and 200 fF for the bitline
capacitance so you can show charge sharing when reading the memory). Using two
of these arrays (8-bit DRAM) design the supporting circuitry to show writing
and reading from the DRAM. This circuitry includes the n-sense amp, p-sense
amp, EQ circuit, and I/O transistors (use two I/O lines). You can use Spice Code
to generate the 4 word line signals, sense amp strobes, EQ, and I/O transistor
control signals. Be sure you are clear showing writing, reading, and refreshing
the memory cell.
HW#2 – due Wednesday, January 27, A16.1, A16.2, and design, layout, and simulate (DC voltage transfer curves and propagation delay vs. load C) a NAND gate made using 10/2 MOSFETs. Show your NAND gate schematic, icon, and layout NCC, DRC, and Well Check without errors.
HW#1 – due Monday, January 25, problem A11.11 and design, layout, and simulate (DC voltage transfer curves and propagation delay vs. load C) a 20/10 inverter. Show your inverter schematic, icon, and layout NCC, DRC, and Well Check without errors.
Projects –
· Grade will be based on a presentation at the end of the semester to the class.
· Your presentation should be in ppt and tutorial in nature.
· I would like to record the presentation and post your ppt in PDF format online (if this is a problem please let me know)
· Use the book’s 50 nm process with a VDD of 1 V
· Presentation length is 30 minutes with and additional 5 minutes for questions
· Due April 28 (email me your ppt and be ready to present in class)
JB – design of all digital DLLs for use in SDRAM (with a focus on what the industry is currently using)
KC – design of charge-pump DLLs for use in SDRAM (benefits for potential use, drawbacks, and concerns)
CC – the use and design of synchronous mirror delays (SMDs) in SDRAM instead of a DLL (with a focus on what industry is currently using)
LM – use of an over-damped PLL in place of DLL in SDRAM. Is this possible or practical? What are the benefits and drawbacks?
SB – the use of self-biasing in the design of PLLs and DLLs
RS – survey of the literature discussing the benefits and drawbacks of the various delay elements used for DLL design (including a detailed reference list)