Memory Circuit Design
Spring 2010, Boise State University
Lecture notes are here
Homework assignments and project information are found here
Current grades are here
Instructor: Jake Baker
Course TA: Qawi Harvard
(Office hours are on TTH from 1 to 2:30 PM in MEC 202 then moving to ET
Time: Mondays and Wednesdays, 5:00 to 6:15 PM
Course dates: Wednesday, January 20 to Wednesday, May 5
Location: MEC 106
Holidays: February 15
(Presidents’ day), March 29
and 31, Spring break from instruction
Final Exam time: Wednesday, May 12, 6 to 8 PM
Course Description: Transistor level design of memory circuits. Memory technologies including DRAM, Flash, MRAM, Glass-based, and SRAM will be discussed. A practical introduction to the design of memory circuits. PREREQ: ECE 510 or 410.
Textbooks: CMOS Circuit Design, Layout and Simulation, Revised Second Edition (Chapters 16-19), and
DRAM Circuit Design: Fundamental and High-Speed Topics by Keeth, Baker, Johnson, and Lin
20% Homework and class participation
20% Mid-term test
Email questions should be sent to the course’s Google group (not directly to the instructor). While the instructor may likely respond quickly (to make getting the credit for the class participation challenging) questions for the instructor (only) should be asked in person during his office hours.
No laptops or Internet appliances can be used during lectures.
No late work accepted. All assigned work is due at the beginning of class.
Neither the final exam nor final project will be returned at the end of the semester.
Regularly being tardy for lectures, leaving in the middle of lectures, or earlier from lectures is unacceptable without prior consent of the instructor
Cheating or plagiarism will result in an automatic F grade in the course (so do your own homework and projects!)