ECE 5/418 Memory Circuit Design
Fall 2008, Boise State University
Homework assignments and project information are found here
Instructor: Jake Baker
Time: 6:30-7:45 pm, MW from Monday, August 25 to Wednesday, December 10.
Room: MEC 307
September 1 (Labor day), Monday/Wednesday, Nov. 24 and 26 (Thanksgiving)
Extra lectures: Friday, Sept. 5 from 5 to 6:15 pm in MEC 307.
Final exam time: Wednesday, December 10, 6 to 8 pm
Course Description: Transistor level design of memory circuits. Memory technologies including DRAM, Flash, MRAM, Glass-based, and SRAM will be discussed. A practical introduction to the design of memory circuits. PREREQ: ECE 510 or 410.
Textbooks:†††† CMOS Circuit Design, Layout and Simulation, Revised Second Edition (Chapters 16-19), and
DRAM Circuit Design: Fundamental and High-Speed Topics by Keeth, Baker, Johnson, and Lin
5% Class participation
20% Mid-term test
Email questions should be sent to the courseís Google group (not directly to the instructor). While the instructor may likely respond quickly (to make getting the credit for the 5% class participation challenging) questions for the instructor (only) should be asked in person during his office hours.
No laptops or Internet appliances can be used during lectures.
No late work accepted. All assigned work is due at the beginning of class.
Neither the final exam nor final project will be returned at the end of the semester.
Regularly being tardy for lectures, leaving in the middle of lectures, or earlier from lectures is unacceptable without prior consent of the instructor
Cheating or plagiarism will result in an automatic F grade in the course (so do your own homework and projects!)