ECE 5/411 CMOS Analog IC Design
Fall 2009, Boise State University

 

The CMOSedu.com Google groupís (http://groups.google.com/group/cmosedu) and the email address is CMOSedu@googlegroups.com

 

Lecture notes are here

Homework assignments, project information, and due dates are found here

Current grades are here


Instructor: Jake Baker

Time: 4:40-5:55 pm, MW from Monday, August 24 to Wednesday, December 9.

Textbook: CMOS Circuit Design, Layout and Simulation, Revised Second Edition (Chapters 9, 20-24)
Room: MEC 206

Holidays: Monday, Sept. 7 (Labor day), Wednesday, Nov. 11 (we will observe Veteranís day in this course), and Monday/Wednesday, Nov. 23 and 25 (Thanksgiving)
Final exam time:
 Monday, Dec. 14, 6 to 8 PM

Course description: Design, layout, and simulation of CMOS analog integrated circuits. Current mirrors, voltage and current references, amplifiers, and op-amps. PREREQ: ECE 510 or 410

 

Grading
15% Homework

5% Class participation
20% Test1
20% Test2
20% Project 
20% Final

 

Email questions should be sent to the courseís Google group (not directly to the instructor). While the instructor may likely respond quickly (to make getting the credit for the 5% class participation challenging) questions for the instructor (only) should be asked in person during his office hours.

 

Policies

No laptops or Internet appliances can be used during lectures.

No late work accepted. All assigned work is due at the beginning of class.

Neither the final exam nor final project will be returned at the end of the semester.

Regularly being tardy for lectures, leaving in the middle of lectures, or earlier from lectures is unacceptable without prior consent of the instructor

Cheating or plagiarism will result in an automatic F grade in the course (so do your own homework and projects!)

 

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