ECE 5/411 CMOS Analog IC Design
Fall 2008, Boise State University


The Google groupís ( and the email address is


Homework assignments and project information are found here

Lecture notes are here

Current grades are here

Instructor: Jake Baker

Time: 4:40-5:55 pm, TuTh from Tuesday, August 26 to Thursday, December 11.

Textbook: CMOS Circuit Design, Layout and Simulation, Revised Second Edition (Chapters 9, 20-24)
Room: MEC 206

Holidays: Tuesday, Nov. 11 (we will observe Veteranís day in this course), and Tuesday/Thursday, Nov. 25 and 27 (Thanksgiving)
Final exam time:
 Thursday, December 11 from 4:40 to 5:55 pm

Course description: Design, layout, and simulation of CMOS analog integrated circuits. Current mirrors, voltage and current references, amplifiers, and op-amps. PREREQ: ECE 510 or 410


15% Homework

5% Class participation
20% Test1
20% Test2
20% Project 
20% Final


Email questions should be sent to the courseís Google group (not directly to the instructor). While the instructor may likely respond quickly (to make getting the credit for the 5% class participation challenging) questions for the instructor (only) should be asked in person during his office hours.



No laptops or Internet appliances can be used during lectures.

No late work accepted. All assigned work is due at the beginning of class.

Neither the final exam nor final project will be returned at the end of the semester.

Regularly being tardy for lectures, leaving in the middle of lectures, or earlier from lectures is unacceptable without prior consent of the instructor

Cheating or plagiarism will result in an automatic F grade in the course (so do your own homework and projects!)