ECE 5/411 CMOS
Analog IC Design
Fall 2007, Boise State University
Homework assignments and project information are found here
Current grades are here
Instructor: Jake Baker
Course TA: TBA
Time: Mondays and Wednesdays from 5:00 – 6:15 from Monday, August 27 to Wednesday, December 12
Circuit Design, Layout and Simulation, (Second Edition)"
Room: MEC 206
September 3 (Labor day), and
Monday/Wednesday, Nov. 19, 21 (Thanksgiving)
Final exam time: Monday December 17 from 8:15 to 10:15 pm
Topics: MOSFET models for analog circuit design, current sources, layout, matching, amplifiers, references, biasing, amplifier and op-amp design.
Prerequisite: ECE 5/410 IC Physical Design
Policies: No late work accepted. Course final exam and project are not returned at the end of the semester. Homework is due at the beginning of the lecture.
For Graduate credit (ECE 511): a more complex project will be assigned and (sometimes) an additional exam problem will given.