ECE 5/410 Integrated Circuit Physical Design
Spring 2010, Boise State University

 

The CMOSedu.com Google group’s (http://groups.google.com/group/cmosedu) and the email address is CMOSedu@googlegroups.com

 

Lecture notes are here

Homework assignments, project information, and due dates are located here

Current grades are here

  

Textbook: CMOS Circuit Design, Layout and Simulation, Revised Second Edition (Chapters 1-6, 10-15, 18)
Instructor: Jake Baker
Time: Mondays and Wednesdays, 6:45 to 8 PM (note the 15 minute shift later from the printed schedule)

Course dates: Wednesday, January 20 to Wednesday, May 5

Location: MEC 106

Holidays: February 15 (Presidents’ day), March 29 and 31, Spring break from instruction
Final Exam time: Monday, May 10, 6 to 8 PM

Course content – An introduction to CMOS IC design, layout, and simulation. MOSFET operation and parasitics. Digital design fundamentals, design of digital logic blocks. PREREQ: ECE 322. COREQ ECE 323.

For Graduate credit (ECE 510): a more complex project will be assigned and (sometimes) an additional exam problem will given.

 

For the fabrication of chips in this class, On Semiconductor 500 nm (C5 with two polysilicon layers and 3 levels of metal) will be used with a MOSIS technology code of SCN3ME_SUBM with a lambda of 300 nm.

MOSIS information for this process is located here and the SPICE models are C5_models.txt

In this course we will make extensive use of LTspice for SPICE simulation and Electric for layout and schematics (Electric video tutorials).

Layout examples using Electric from the lectures are found in ece5410_s10.jelib.

 

Grading
15% Midterm1
15% Midterm2
15% Homework and class participation (in class and via the Electric and CMOSedu Google groups)

15% Quizzes
20% Project
20% Final

 

Email questions should be sent to the CMOSedu google group (not directly to the instructor).

While the instructor may likely respond quickly (to make getting the credit for the class participation challenging) questions

for the instructor (only) should be asked in person during his office hours.

 

Policies

No laptops or Internet appliances can be used during lectures.

No late work accepted. All assigned work is due at the beginning of class.

Neither the final exam nor final project will be returned at the end of the semester.

Regularly being tardy for lectures, leaving in the middle of lectures, or earlier from lectures is unacceptable without prior consent of the instructor

Cheating or plagiarism will result in an automatic F grade in the course (so do your own homework and projects!)

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