Integrated Circuit Physical Design
Spring 2009, Boise State University
Lecture notes are here
Homework assignments, project information, and due dates are located here
Current grades are here
For the fabrication of chips in this class, On Semiconductor 500 nm (C5 with two polysilicon layers and 3 levels of metal) will be used with a MOSIS technology code of SCN3ME_SUBM with a lambda of 300 nm.
Layout examples using Electric from the lectures are found in ece5410_s09.jelib.
Textbook: CMOS Circuit
Design, Layout and
Simulation, Revised Second Edition (Chapters 1-6, 10-15, 18)
Instructor: Jake Baker
Time: Tuesdays and Thursdays, 12:10 to 1:25 PM
Course dates: Tuesday, January 20 to Thursday, May 7
Location: MEC 307
Holidays: March 24 and 26,
Spring vacation from
Final Exam time: Tuesday, May 12, 1 to 3 PM
Course content – An introduction to CMOS IC design, layout, and simulation. MOSFET operation and parasitics. Digital design fundamentals, design of digital logic blocks. PREREQ: ECE 322. COREQ ECE 323.
For Graduate credit (ECE 510): a more complex project will be assigned and (sometimes) an additional exam problem will given.
Class participation (in class and via the Electric and CMOSedu Google
Email questions should be sent to the CMOSedu google group (not directly to the instructor).
While the instructor may likely respond quickly (to make getting the credit for the 5%
class participation challenging) questions for the instructor (only) should be asked in person
during his office hours.
No laptops or Internet appliances can be used during lectures.
No late work accepted. All assigned work is due at the beginning of class.
Neither the final exam nor final project will be returned at the end of the semester.
Regularly being tardy for lectures, leaving in the middle of lectures, or earlier from lectures is unacceptable without prior consent of the instructor
Cheating or plagiarism will result in an automatic F grade in the course (so do your own homework and projects!)