.options reltol=0.01 abstol=1P vntol=1U scale=.3u VDD VDD 0 DC 5 VREFP VREFP 0 DC 5 VREFM VREFM 0 DC 0 VCIN CIN 0 DC 0 VinA VinA 0 DC 0 Sin 0.75 0.75 7MEG VinB VinB 0 DC 0 Sin 0.75 0.75 3.5MEG Vclock clock 0 DC 0 Pulse 0 5 0 200p 200p 4.8n 10n .tran 1n 300N 10N UIC RF VOUTF VOUT 10K CF VOUT 0 1P XADC1 VDD VREFP VREFM VinA A7_ A6 A5 A4 A3 A2 A1 A0 clock ADC8bit XADC2 VDD VREFP VREFM VinB B7_ B6 B5 B4 B3 B2 B1 B0 clock ADC8bit XINVMSBA A7_ A7 VDD INVERT XINVMSBB B7_ B7 VDD INVERT XINVMSBSUM SUM8 SUM8_ VDD INVERT XDAC VDD VREFP VREFM VoutF SUM8_ SUM7 SUM6 SUM5 SUM4 SUM3 SUM2 SUM1 SUM0 DAC9bit *** START OF INVERTER SUBCIRCUIT*************************** .SUBCKT INVERT A A_ VDD M1 A_ A 0 0 NMOS L=2 W=10 M2 A_ A VDD VDD PMOS L=2 W=30 .ENDS *** START ADC Subcircuit *********************************** .subckt ADC8bit VDD VREFP VREFM Vin B7 B6 B5 B4 B3 B2 B1 B0 CLOCK * Set up common mode voltage BCM VCM 0 V=(V(VREFP)-V(VREFM))/2 * Set up logic switching point R3 VDD VTRIP 100MEG R4 VTRIP 0 100MEG * Ideal input sample and hold XSH VDD VTRIP VIN OUTSH CLOCK SAMPHOLD * Level shift by VREFM and 1/2LSB BPIP PIPIN 0 V=V(OUTSH)-V(VREFM)+((V(VREFP)-V(VREFM))/2^9) * 8-bit pipeline ADC X7 VDD VTRIP VCM PIPIN B7 VOUT7 ADCBIT X6 VDD VTRIP VCM VOUT7 B6 VOUT6 ADCBIT X5 VDD VTRIP VCM VOUT6 B5 VOUT5 ADCBIT X4 VDD VTRIP VCM VOUT5 B4 VOUT4 ADCBIT X3 VDD VTRIP VCM VOUT4 B3 VOUT3 ADCBIT X2 VDD VTRIP VCM VOUT3 B2 VOUT2 ADCBIT X1 VDD VTRIP VCM VOUT2 B1 VOUT1 ADCBIT X0 VDD VTRIP VCM VOUT1 B0 VOUT0 ADCBIT .ends * Ideal Sample and Hold subcircuit .SUBCKT SAMPHOLD VDD VTRIP Vin Vout CLOCK Ein Vinbuf 0 Vin Vinbuf 100MEG S1 Vinbuf VinS VTRIP CLOCK switmod Cs1 VinS 0 1e-10 S2 VinS Vout1 CLOCK VTRIP switmod Cout1 Vout1 0 1e-16 Eout Vout 0 Vout1 0 1 .model switmod SW .ends * Pipeline stage .SUBCKT ADCBIT VDD VTRIP VCM VIN BITOUT VOUT S1 VDD BITOUT VIN VCM switmod S2 0 BITOUT VCM VIN switmod Eouth Vinh 0 VIN VCM 2 Eoutl Vinl 0 VIN 0 2 S3 Vinh VOUT BITOUT VTRIP switmod S4 Vinl VOUT VTRIP BITOUT switmod .model switmod SW .ends *** END ADC Subcircuit ************************************** *** Start Ideal DAC Subcircuit ****************************** .subckt DAC9bit VDD VREFP VREFM Vout B8 B7 B6 B5 B4 B3 B2 B1 B0 *Generate Logic switching point, or trip, voltage R1 VDD trip 100MEG R2 trip 0 100MEG *Change input logic signals into logic 0s or 1s X8 trip B8 B8L Bitlogic X7 trip B7 B7L Bitlogic X6 trip B6 B6L Bitlogic X5 trip B5 B5L Bitlogic X4 trip B4 B4L Bitlogic X3 trip B3 B3L Bitlogic X2 trip B2 B2L Bitlogic X1 trip B1 B1L Bitlogic X0 trip B0 B0L Bitlogic *Non-linear dependent source, B, for generating the DAC output Bout Vout 0 V=((v(vrefp)-v(vrefm))/512)*(v(B8L)*256+v(B7L)*128+v(B6L)*64+ +v(B5L)*32+v(B4L)*16+v(B3L)*8+v(B2L)*4+v(B1L)*2+v(B0L))+v(vrefm) .ends .subckt Bitlogic trip BX BXL Vone one 0 DC 1 SH one BXL BX trip Switmod SL 0 BXL trip BX Switmod .model switmod SW .ends *** END DAC Subcircuit ************************************* .control destroy all run PLOT VINA VINB VOUT .endc