LASI Schematic and Layout Examples using the MOSIS Design Rules

AMI Semiconductor (AMIS) in Pocatello, Idaho provides educational support for MOSIS and europractice multiproject wafers. The MOSIS educational program (MEP) participants can select between AMIS's AB and C5 CMOS processes. See here for more information.

In the AB process, a 1.5 um process with the scaling factor, lambda, of 0.8 um (using the SCMOS rules used in the MOSIS LASI setups, mosis.zip here). Minimum poly is 2*lambda or 1.6 um (and so minimum device Ldrawn is 1.6 um) The MOSIS site has SPICE and other information. For design rule checking using LasiDrc and the file Mosis_scmos.drc (the SCMOS rules). The MOSIS technology code is SCNA with lambda of 0.8.

In the C5 process, a 0.5 um process with the scaling factor, lambda, of 0.3 um. Minimum poly is 2*lambda or 0.6 um (and so minimum device Ldrawn is 0.6 um) The MOSIS site has SPICE and other information. For design rule checking using LasiDrc use the file Mosis_subm.drc. The MOSIS technology code is SCN3ME_SUBM with lambda of 0.3.

When using LasiCkt
- the footer file contains the SPICE models (right click on link to save), ami_abn_corner_bsim3.txt or ami_c5n_corner_bsim3.txt
- the header file contains the type of analysis, any command scripts, options, etc.
- all of the header files below use a .options scale factor of 0.3 um (for the C5 process)
- the below examples are for use with WinSPICE or HSPICE (hspice_info.txt).

Right click on the links to save target

• Nmos_id_vds.tld (schematic for ID vs VDS plots) and the header Nmos_id_vds_hdr.txt
• Pmos_id_vsd.tld (schematic for ID vs VSD plots) and the header Pmos_id_vsd_hdr.txt
• Nmos_id_vgs.tld (schematic for ID vs VGS with varying VSB) and the header Nmos_id_vgs_hdr.txt
• Pmos_id_vsg.tld (schematic for ID vs VGS with varying VSB) and the header Pmos_id_vsg_hdr.txt
• Layout of some NMOS and PMOS transistors is Mos_lay.tld
• Inverter.tld (schematic) and Inverter_lay.tld (layout)
• Transmission gate Tg.tld and Tg_lay.tld
• Nand.tld and Nand_lay.tld
• Bias_ckts.tld, Bias_ckts_lay.tld, and Bias_ckts_hdr.txt (analog bias circuit using an off-chip resistor)
• Ring_osc.tld, Ring_osc_lay.tld, and Ring_osc_hdr.txt (9-stage ring oscillator)
• Comparator_sims.tld, Comparator_sims_lay.tld, and Comparator_sims_hdr.txt (a wide-swing comparator)
• Adder_sims.tld, Adder_sims_lay.tld, and Adder_hdr.txt (a static CMOS adder)
• Up_down_count_sims.tld, Up_down_count_sims_lay.tld, and Count_hdr.txt (an up/down counter with preset)

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CMOS Mixed-Signal Circuit Design

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