CMOS Circuit Design, Layout, and
Simulation
· Errata
· Why are HW solutions to “CMOS” posted at CMOSedu?
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1. Can you show a start-up circuit for the BGR in Fig. 23.27?
2. Is gm (and thus device fT) independent of overdrive voltage in nanometer CMOS?
3. In Chapter 20 Pg 629 Fig 20.22 I am not clear of the reason Vreg…
4. Why do you call the reference in fig. 20.14 a Beta-Multiplier Reference (BMR)
5. Reading about "hot carriers" I found your explanation that this had to do…
6. On pages 144 and 145 you discuss how VDS,sat is not exactly VGS-VTHN. Why
8. How do define we VDS,sat for short-channel MOSFETs?
9. SF gain calculations on page 670 and 691
10. In Fig. 26.41 it says this is NOT the way to implement GE in ...
11. In Fig. 26.16 can’t we remove the phi2 switches on the bottom of C2 for better operation?
12. I tried to hand calculate the values in Table 9.2 using the short channel equations...
13. I had a quick question on deriving voltage gain on common-source amp with source degeneration.
14. Are the PMOS loads in Fig. 24.21 called "composite cascodes?"
15. What does "feature size" mean?
16. Would you provide a reference for the Miller Effect?
17. Why does the spectrum analyzer block diagram...?
18. In the square-law equation you use (VDS - VDS,sat) while others...
19. On page 1146 in the third paragraph you indicate you can't use the ...
20. What is the layer "elec" in the NCSU setups for the C5 process?